AMD RyZen CPU Architecture for 2017

Discussion in 'PC Industry' started by fellix, Oct 20, 2014.

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  1. Anarchist4000

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    Probably not until CES if that's when they actually launch. Doubtful anyone beyond some select partners would actually have devices to test until then. Maybe we get some architecture details, but doubt there is much along the lines of independent performance benchmarks.
     
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  2. monstercameron

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  3. cheapchips

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    I can't help but pronounce it raisin when I read that. Seems like a missed opportunity. You could call multithreading 'grapevine'.

    ...I've not got the hang of marketing to the PC master race have I? :)

    XFR sounding interesting. It's ages since I bothered oc'ing anything, but doesn't it make having an over clocked machine much more power efficient?
     
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  4. Alexko

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    So it's 3.4+GHz, which probably means that 3.4GHz is the base clock. It ought to turbo up to 3.6GHz or perhaps a bit more. I think Zen will do fairly well.
     
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  5. fehu

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    16 thread at 3.4GHz
    I remember my reaction when first heard about sun's niagara
     
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  6. ninelven

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    Whaaaaa? No pricing info is disappointing. On par with, maybe slightly better than 6900K, at a lower TDP which is excellent. But if it is a 1k+ processor, not really that remarkable. I'm assuming it will come in less than that given how much they harped on the price of the Intel chip, but then they didn't provide any pricing details or even hints themselves so...

    Also don't really get the name.... Zen was simple and classy, no need to change it IMHO. Other than that, it looks very promising (assuming they don't price gouge like Intel).
     
  7. 3dilettante

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    I'll include this link since it has the most complete slide set I've encountered:
    http://www.anandtech.com/show/10907...nvme-neural-net-prediction-25-mhz-boost-steps

    The overall concept neural net branch prediction isn't new, since perceptron predictors have already been used in prior AMD CPUs.
    The hashed version seems to be different, but in what way is not clear. There are weaknesses from Agner's optimization document, such as nested loops not doing particularly well, and research showing that perceptron predictors don't do well with patterns that are not linearly separable yet generally predictable (alternating taken/not taken).
    A hashed perceptron might do more to detect these cases and route them to different predictors or somehow separate out components of them so that the perceptron can more readily digest the components.

    The prediction for instruction routing inside the core is unclear, but might have to do with predictors for routing ops to certain schedulers or timing their issue. At some level, it might help if the individual schedulers cannot readily communicate or immediately forward results between themselves. Something like a predictor for what architected registers tend to hold up dependent ops could allow them to route to one set of lanes over the other. Other cases involve possible issue port conflicts, where instructions issued based on age might wind up contending for a specific port more than they need to, although the simple operations are well-distributed and fast on the integer side pictured. Some complex ops and perhaps inter-thread contention might make this useful.

    It might also plug into the power management scheme, if things like the schedulers, uop cache, or issue queue can keep some limited history of what gaps might open up for a given run of operations, or how sensitive they are to clock-gating or duty cycling.
    The fine-grained clock management might be finer at a unit level with those.

    The prefetch item is curious. There was talk of a pattern-based prefetcher in Bulldozer, which basically went unmentioned ever since. Perhaps this is a new version.
    Involving that whole Load/Store and LD1 block is uncertain for prefetching, particularly the queues.
    One exception, possibly, is stack accesses. Perhaps some of the relative addressing there can be handled more speculatively and the stack engine can prefetch and pre-calculate simple strides without overly polluting the queues (maybe take some load of the AGUs?).
     
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  8. Dave Baumann

    Dave Baumann Gamerscore Wh...
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    Zen is already publicised as the Architecture name, which will span different classes/targets of product .
     
  9. ninelven

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  10. xEx

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    Zen is the name of the arch. Ryzen is the name of the platform that use that arch. I actually really like the name and its hidden meaning(risen).

    I was really impressive by the presentation I was skeptical but now I'm optimistic and it seems that AMD have a product to really risen themselves finally, we will see if(in that case) they have the knowledge and expertise to use it.
     
  11. ninelven

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    I know that. As does 99%+ of the people on this forum...

    ...well, maybe not anymore.


    Example of a clean name: Zen A14, Zen C27, Zen S84

    Zen - the architecture, A for APUs, C for Consumer chips, S for server chips (could use P for professional... whatever). Performance number = Cores x Clock (in GHz). Clean.

    Or if you prefer more self documenting names: Zen A 4x3.2, Zen C 8x3.4, Zen S 32x2.6
     
    #551 ninelven, Dec 14, 2016
    Last edited: Dec 14, 2016
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  12. xEx

    xEx
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    Well I'm sure Dave will pass your suggestions to the marketing department :p. Iisa said that they have been reading the comments so maybe you can name the new cpus if they like your idea.

    Enviado desde mi HTC One mediante Tapatalk
     
  13. tunafish

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    It's been confirmed that the integer side of Zen has 6 individual schedulers, and once an op has been dispatched to a scheduler, it can only be issued to the ALU/AGU that is attached to that scheduler. The advantage of this method is that it's much easier and cheaper to implement the large queues needed for large instruction windows, the downside is that if your workload gets dispatched sub-optimally, you can lose out in scheduling efficiency.

    It seems to me that this prediction is meant to alleviate this problem. They probably have some way of predicting which schedulers each op should be issued to avoid bubbles.
     
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  14. itsmydamnation

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    You cant trademark the word Zen, Ryzen has grown on me over the last day at first i didn't think much.
     
  15. Gubbi

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    Dispatch is one thing, the other problem in not using a global scheduler is that you instruction window is partitioned according to instruction type/exec unit. If you have dependend loads (linked lists) and you miss the D$ on the first load, you quickly fill up your LS queue with stalled instructions. Then an independent load comes along and can't dispatch because the queues are full.

    Example: A loop that looks up stuff in a dictionary, where each hashed entry points to a linked list of 1-10 elements. Missing the first element in the linked list cause all subsequent loads to stall and sit dead in the queue, if the same happens on the same second iteration of your loop you're quickly running out of LS queue slots. With A global scheduler, you schedule the first load for execution The subsequent dependent loads would then sit idle in the ROB until the first load completes. The outer loop would grind on, because traversing each hash slot is independent and we have plenty of ROB ( ~200 )entries to keep things going.

    Unless there is a shit ton of LS queue entries, I'd expect Zen to have pathological cases where Intel beats it handsomely.

    Cheers
     
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  16. ninelven

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    Yeah, lots of competitors in the x86 market who might jump on the Zen naming bandwagon....

    Last time I checked "core" is word too....
     
  17. Blazkowicz

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    Asus is using "Zen" related trademarks a lot : Zenphone, Zenpad, Zenbook (with some capitalization in the middle).

    Otherwise trademark law seems generous : if you decide "phone", 'pod", "play" or even "word" or "maps" can't be a trademark then some companies would be in trouble?
     
  18. digitalwanderer

    digitalwanderer Dangerously Mirthful
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    One question though, why were they mispronouncing it as RYE-ZEN all during that presentation? Shouldn't it be Riss-Zen if it's named after Rys? I'mma gonna make some calls and shoot out a few e-mails...
     
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  19. turkey

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    I assumed it was tied to Horizon and how you pronounce that which was the name of the presentation.

    I have not looked into the name any further than watching the stream so perhaps I have missed quite a bit.
     
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  20. xEx

    xEx
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    I'm assuming they want it to be associate to risen.
     
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