Bondrewd
Veteran
Yeah it uses a dogshit cheap (costs like 6 bucks to make) InFO-R fanout with class leading 30um pitch.that AMD does not use elevated fan-out bridges as first reported by some outlets, but indeed some InFO-R variant without a local silicon interconnect
The entire N3x lineup gimmick is that each part is dogshit cheap to make.
Pretty sure Intel quoted higher figures of MDIO over EMIB in SPR and that's lotta lines extending rather low clocked (low 3s GHz) mesh.the quoted 0.4pJ/bit would be on the very high end for relatively low clocked silicon bridge connections with a lot of lines
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