AMD: RDNA 3 Speculation, Rumours and Discussion

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There's nothing to 'emulate' in tensor/xmx/matrix cores, they're just accelerating normal matrix math. As for precision, RDNA2 goes all the way down to 8:1 INT4 so yeah, you can pick lower precisions for inferencing if you want.
To be honest I read emulation of fixed function units more like emulating ROPs, presumably accelerating rendering in higher resolutions, while using less die space. Don't know why my mind thought of that, probably because tensor cores are anything but fixed function.
 
Keep any rumors and speculations before hand in this thread.

During and after the reveal the new discussion thread to use is here:

 
b3da052.png


Quick and dirty die areas derived from the low-resolution Angstronomics picture.
I agree with your first set of numbers for GCD and MCD (they are very close to the ones Angstronomics told us a while ago [305mm² and 37.5mm², respectively]). But what is the "molding overhead" supposed to be? The visible edges of the dies in the mold are the real edges of the dies as cut from the wafer.
 
I agree with your first set of numbers for GCD and MCD (they are very close to the ones Angstronomics told us a while ago [305mm² and 37.5mm², respectively]). But what is the "molding overhead" supposed to be? The visible edges of the dies in the mold are the real edges of the dies as cut from the wafer.
Discussion starts here:


with Dave Baumann providing an official comment, demonstrating that (not for the first time) measurements of a packaged die are always too large. 0.5mm is just an approximate correction...

Of course I could re-do my die-size estimates based on the dimensions stated by the website (308 and 37.5mm²) with a correction of the linear dimensions by 0.5mm: e.g. 289.7mm² and 31.6mm²; we'll get much better numbers at some point :)
 
Discussion starts here:


with Dave Baumann providing an official comment, demonstrating that (not for the first time) measurements of a packaged die are always too large. 0.5mm is just an approximate correction...

Of course I could re-do my die-size estimates based on the dimensions stated by the website (308 and 37.5mm²) with a correction of the linear dimensions by 0.5mm: e.g. 289.7mm² and 31.6mm²; we'll get much better numbers at some point :)
Dave's comment alluded to the "official" size (scare quotes are in the original) of a specific chip (RV740), probably as designed, before taking the extra space needed for dicing into account and in my opinion doesn't really relate to your 0.5mm here.
The comparison was with a obviously quite rough measurement of some guy at hexus.net, who only said (rounded?) 12mmx15mm for the die dimensions. "Official" was 170mm² according to Dave. That could have been 11.62mm x 14.63mm for all we know. Then add let's say 50µm for the (dicing strait - scribe line width)* and we would have ended up with 11.67mm x 14.68mm as the actual physical die with a careful measurement.
Or maybe the difference between the "pre-silicon number" and the "final 'official' size" is the area required for the dicing? That would be pretty much exactly 0.15mm (150µm) in this case (from 2009). Hey, that fits pretty well with my number below I wrote before adding this spoiler! ;)

*: depending on how the dicing is actually done, the subtraction may not be warranted as the wafer may not be cut through completely. In that case one can usually see a small step on the side of the dies (not for N31 of course, because of the mold).
0.5mm may be a rule of thumb if one does a very crappy measurement with a caliper and measures not just the die but includes some underfill "leaking" out of the sides of the die in the measurement.
0.5mm is way too much for the necessary dicing strait/scribe line width between dies. More common should be 100µm or maybe slightly more, but definitely below 0.2mm (and a part of that is removed during dicing, so would not be included in the photo). In the end, who cares about how much less space the design takes from the outer dimensions of the die? AMD, intel, and nV do, for sure, but not we. They have to pay for the whole area of the wafer (including the space needed for dicing). If some company wants to leave 1mm space between dies, TSMC will let them do that, but that would be quite a waste of money.

Anyway, my point was that one actually sees the actual edges of the physical die in that photo. And that are the important dimensions (especially for the costs). That's why you should simply stick to your first set of number (~303mm² and 36mm²) and not apply some (misguided) "corrections". Your "uncorrected" numbers are probably closer to the correct ones (assuming the given package dimensions are correct). ;)
 
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Dave's comment alluded to the "official" size (scare quotes are in the original) of a specific chip (RV740), probably as designed, before taking the extra space needed for dicing into account and in my opinion doesn't really relate to your 0.5mm here.
The comparison was with a obviously quite rough measurement of some guy at hexus.net, who only said (rounded?) 12mmx15mm for the die dimensions. "Official" was 170mm² according to Dave. That could have been 11.62mm x 14.63mm for all we know. Then add let's say 50µm for the (dicing strait - scribe line width)* and we would have ended up with 11.67mm x 14.68mm as the actual physical die with a careful measurement.
Or maybe the difference between the "pre-silicon number" and the "final 'official' size" is the area required for the dicing? That would be pretty much exactly 0.15mm (150µm) in this case (from 2009). Hey, that fits pretty well with my number below I wrote before adding this spoiler! ;)

*: depending on how the dicing is actually done, the subtraction may not be warranted as the wafer may not be cut through completely. In that case one can usually see a small step on the side of the dies.
0.5mm may be a rule of thumb if one does a very crappy measurement with a caliper and measures not just the die but includes some underfill "leaking" out of the sides of the die in the measurement.
0.5mm is way too much for the necessary dicing strait/scribe line width between dies. More common should be 100µm or maybe slightly more, but definitely below 0.2mm (and a part of that is removed during dicing, so would not be included in the photo). In the end, who cares about how much less space the design takes from the outer dimensions of the die? AMD, intel, and nV do, for sure, but not we. They have to pay for the whole area of the wafer (including the space needed for dicing). If some company wants to leave 1mm space between dies, TSMC will let them do that, but that would be quite a waste of money.

Anyway, my point was that one actually sees the actual edges of the physical die in that photo. And that are the important dimensions (especially for the costs).

The issue is that the smaller the die area, the larger the impact the measurement error has upon the die area. The error, whatever it turns out to be for the small die, is looking to be quite substantial...

Also, when looking at die shots such as:


you'll usually see that there is, indeed, a non-functional perimeter to dies - and that's after sawing. When talking about costs or performance per unit area there's just a bit more error because of that - but costs should be based upon wafer layout for the chips (and yields).

There could be 300+ chips difference for a 12" wafer for this small die according to:


based upon 7.4x5.1 versus 6.9x4.6mm (adjusted by me from the Angstronomics numbers - not those derived and adjusted by me from the picture) = 1636 versus 1949...

I expect the real dimensions to be somewhere between my low estimate and the approximate Angstronomics numbers - originally they come with a "~" :)
 
The issue is that the smaller the die area, the larger the impact the measurement error has upon the die area. The error, whatever it turns out to be for the small die, is looking to be quite substantial...

Also, when looking at die shots such as:


you'll usually see that there is, indeed, a non-functional perimeter to dies - and that's after sawing. When talking about costs or performance per unit area there's just a bit more error because of that - but costs should be based upon wafer layout for the chips (and yields).
Actually, if you look at the pictures with the right lighting, one can see there is almost no space left at all. ;)
How thick is a typical wafer? Depending on what you do, it is often about 0.7mm, isn't it? That means there is less than 100µm (50µm?) space from the edge of the die in the following pictures.
That's a 7nm design from AMD (PS5):
amd_7nm_die_edgeps5vufq7.jpg


And this a 16nm AMD chip (XB1-S):
16nm_die_edge4zepq.jpg


Here you can also nicely see the the small edge on the side of the die caused by the different dicing method I mentioned earlier. :)

The dicing area is sometimes used for test structures for wafer leving testing (they get partially destroyed by dicing). But in these photos the functional structures of the chip extend extremely close to the actual edge of the die.
 
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Actually, if you look at the pictures with the right lighting, one can see there is almost no space left at all. ;)
How thick is a typical wafer? Depending on what you do, it is often about 0.7mm, isn't it? That means there is less than 100µm (50µm?) space from the edge of the die in the following pictures.
That's a 7nm design from AMD (PS5):
amd_7nm_die_edgeps5vufq7.jpg


And this a 16nm AMD chip (XB1-S):
16nm_die_edge4zepq.jpg


Here you can also nicely see the the small edge on the side of the die caused by the different dicing method I mentioned earlier. :)

The dicing area is sometimes used for test structures for wafer leving testing (they get partially destroyed by dicing). But in these photos the functional structures of the chip extend extremely close to the actual edge of the die.
Added street markings, rough yellow and red lines. I wasn't super precise but you can make out the streets due to the pads.
Edit- I'm not sure how big streets are on modern processes/wafers. I mostly dealt with +130nm 8in wafers down to maybe 40nm 12in wafers (might have gone down to 28nm, not sure).
 

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This video focuses on how TSMC plans to get past 3nm. A major problem with the coming generations of process technology is that multi-patterning will have to be used for more layers. Multi-patterning slows down the machine, reducing the count of wafers per hour it can produce.

The need for multi-patterning can be reduced by increasing the magnification of the optical system which goes hand in hand with increasing the numerical aperture. The side-effect of the increased magnification is that the reticle area is reduced!

One aspect of the solution is a revised optical system that uses anamorphic projection.

The end result of all this pain (about a decade of pain, it seems) is that you end up with a reticle that's only 16.5x26mm. This appears to imply that the largest conventional chip produced by this process is 429mm².

So it turns out that chiplets are needed simply to avoid crashing into this area limitation. But this problem only becomes real in 2025 or later, it seems? So RDNA 5?...
 
But this problem only becomes real in 2025 or later, it seems?
hNA has been pushed waaaaaaaaay up, think 2027+ timeline for prod steppers.
Just don't think about it for now, really, it's still in voodoo magick stage.

But yes, reticle will be cut in half so vewy complex MCPs are very much the only future left for us all.
 
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