BTW - I am always *very* wary of "stable overclocks". What, exactly, do you consider stable? How do you test that the chip produces the correct results without random errors/artifacts - not just in the paths that are typically stressed, but for all transistors? For example, let's say that for some silly reason, there was either a bit less timing slack or more chip-to-chip variability in the TMU's FP32 Filtering Units which result in small random errors but only for FP32 filtering. It's very unlikely you'd notice that, but at the extreme, it might even end up with failing WHQL tests...
I had personal experience with trying to workaround some really bizarre and nasty HW/process issues in SW for a GPU that worked fine at low frequencies/high voltages, but had some very specific parts not work correctly unless they were clocked/volted much more conservatively than the rest of the chip (which wasn't possible). This resulted in a horrible mix of SW workarounds and/or manually lowering the chip's clocks when certain features were detected as being in use by the driver.
I don't expect such nightmare-ish and extreme process issues to happen on any production PC GPU, but the point remains: "stable overclock" doesn't mean very much IMO. AMD has better tools to figure out what clocks/voltages are safe than we do... it's possible they're doing an awful job at it, but I think it's more likely they need to optimise their hardware design rather than their binning process.