Why do you think that Cayman would be over 400mm² at 40nm?
Why should I believe the rumoured specs of a card whose actual existence and economical feasibility I question in the first place? Seriously, if they really wanted to release another card in that price-segment using the 40nm production process, they'd be better off just taking Cedar and adding a few extra-chip goodies to rectify the 6xxx name tag ...
As I mentioned earlier, if it was supposed to be sweet-spot @ 32nm (let’s shoot low here and assume something along the lines of 280mm2 instead of RV870's rather big 330mm2), it would (at least based on very simplistic mathematical calculation) end up with around 440mm2 @ 40nm.
That doesn't factor in process-specific peculiarities, of course - but in suggesting the 400mm2 mark, I actually already gave AMD’s engineers a lot of credit for possibly reducing the relative size of the (yield-optimized, low-risk) 32nm design by about 10% due to their expert knowledge of the 40nm process
@Mindfury: Looks like those chiphell-guys can't really decide on Caicos' bus width, he?
http://forums.anandtech.com/showpost.php?p=30402647&postcount=497
Quick summary:
- Northern Islands shader is 98.5% as efficient per clock but they can fit 25% more in the same space.
- a new eyefinity
- UVD3 (ati's gpu video decoder)
- new shader model
- thicker PCB for the chip packaging
- changed the voltage regulators buck controllers
- vapor chamber cooler
- 6770 supposed to have relatively low clocks ~700mhz...
- tripling or quadding up on the tessellation power
Anyone care to comment on this? Particularly the SP redesign. The author claims a reduction to 4-wide SPs which allows ATi to fit an additional 25% SPs into each chip. If true, I find it a bit odd as it would give them slightly less mathematical power at the same die size. Cypress: 320x5 = 1600, Cayman: 320(*1.25)x4 = 1600. Seems a bit odd to me, unless there's more to the story or perhaps more SIMDs will be used, increasing the die size.
Anyone care to comment on this? Particularly the SP redesign. The author claims a reduction to 4-wide SPs which allows ATi to fit an additional 25% SPs into each chip. If true, I find it a bit odd as it would give them slightly less mathematical power at the same die size. Cypress: 320x5 = 1600, Cayman: 320(*1.25)x4 = 1600. Seems a bit odd to me, unless there's more to the story or perhaps more SIMDs will be used, increasing the die size.
It can still be worth it if the overall utilization of the new ALU's is higher. This would particularly help those shaders which had lower utilization on older ALU's.
If the rumored parallel setup/raster is true, then 25 simd's is an odd proposition. I'd have expected something that is a multiple of setup/tess units.
The quoted post says 4 of the new ones would have 98.5% the performance of 5 old ones. So they would increase perf./area.
Maybe I'm just too optimistic, but I understood it as "one new 4D is 98.5% as efficient (clock-to-clock) as old 4+1D", but takes only 75% of the spaceSupposedly they are less efficient @ 98.5% throughput compared to the old SP design.
Not so. 25% reduction in SP width is canceled out by 25% increase in SPs, hence my request for comment.
Supposedly they are less efficient @ 98.5% throughput compared to the old SP design.
Not so. 25% reduction in SP width is canceled out by 25% increase in SPs, hence my request for comment.
More like 66,5 mm².I understand it the same way.
btw. the Caicos seems to be about 72mm² large
I doubt the "new shader model" part.
Does anyone remember when D3D10.1 was announced? There is not even a hint about 11.1 yet. Also 10.1 brought some very minor improvements mostly for API orthogonality. D3D11 doesn't seem to need such a minor version upgrade as far as I can tell yet.