Let's hope they've done something to improve the compression, at least.Sadly, while that slide indicates that ROPs have doubled over Juniper, Z-rate per clock hasn't.
Let's hope they've done something to improve the compression, at least.Sadly, while that slide indicates that ROPs have doubled over Juniper, Z-rate per clock hasn't.
80 is a really really nasty number for hardware thread size. If this is true then a whole pile of code that enjoys the "squareness" of 64 or 256 sized workgroups is going to be a nightmare. A total fucking bitch, in fact. Not to mention the mismatch in banks for 32KB of LDS, which doesn't divide into 20s in any meaningful way.One SIMD still has 80 SP's, but now with 4D ALU's, which means that wavefront size has increased to 80.
Why would they do that? 64 was already big, now Branch-Granularity will suck even more compared to GF100.
I don't believe this.
80 is a really really nasty number for hardware thread size. If this is true then a whole pile of code that enjoys the "squareness" of 64 or 256 sized workgroups is going to be a nightmare. A total fucking bitch, in fact. Not to mention the mismatch in banks for 32KB of LDS, which doesn't divide into 20s in any meaningful way.
I don't believe this.
Ok. I want the real one then.
So this picture says, HD6770 can give you 2304 GFLOPS. How is this possible?
320x4 gives you 1280 SPs. So 1280 * 2 FLOP (MADD) * 0,9 GHz is 2073,6 GFLOPS.
FAKE
already in some posts
Another fake, but 80*4 = 64*5, I think there is enough rumors to dismiss the 4D ALUs rumor, it's 5D again, at least for this generation.One SIMD still has 80 SP's, but now with 4D ALU's, which means that wavefront size has increased to 80.
launch is in less than 3 weeks!
It's probably another fake slide.. it's not enough polished to be real.
but if what mao5 is true, that the official pdf are around it won't be much before we get real leaks. It would be about time, launch is in less than 3 weeks!