AMD: R9xx Speculation

In fact,he said R9xx has less SPs than Cypress in Apr,not Cayman.

He only confirmed the scores,not screenshots.

Sometime he was misinformed,but most his leaks turned out to be true.

 

OMG! What kind of thinking is this? The launch presentation for Barts family (according to some people which we may trust in) is ready and this particular shot is called REAL. So, if Barts XT is performance wise approximately as fast as Cypress XT, how may you expect so low TDP?

 

Not only XFX, official Eyefinity PDF says 7680x3200 (that's 6x 2560x1600):

 

One might be surprised...

 

For the reference HD 5700/5800 (therefore Eyefinity models excluded) it is.

 

Exactly. The chart is correct because they have not announced an HD6xxx eyefinity 6 card yet.

 

but I thought the new Eyefinity could do more with their 5 displays?

the chart is bull.

 

ridiculous

 

I don't think it's the best word that can describe that...

http://semiaccurate.com/forums/showthread.php?p=71437#post71437

 

1. It's real
2. It's 1 hour of Photoshop work
3. It's 30 minutes of PowerPoint work

nApoleon said it's real. (1.)
gkar1 said it's real. (1.)
265586888 said it's real deal too. (1.)

mao5 said it's ridiculous (isn't that the magic formula from Harry Potter?). (2.)
LordEC911 said that one might be surprised. (3.)
neliz said it's the kind of bull. (2.)

1. wins

 

I like your methods for running these predictions!

 

I actually believe that you have another PDF.

But given AMDs proficiency in creating a lot of smoke and deliberate distraction, even their currently circulating "official" slides might just be another piece of planned misinformation ...

At this point, I wouldn't trust any spec table presented to me - even if an ever-so-trustworthy AMD marketing professional came to my house to personally inform me about the upcoming cards

 

And what will happen if that marketing person comes with an actual card confirming that Barts is 6700 series and actually has the leaked specifications?

 

I wouldn't call it outright fake, but hard to believe. Unlike others I've always argued that in theory non-pot simd width should be doable (as long as it's a multiple of 4). So I don't think the simd width 20 / thread size 80 this slide implies is impossible, but there is a difference between what is possible and what actually makes sense, and I'm certainly not convinced increasing thread size (which was already twice as large as what nvidia has) further (and to a npot size no less) makes sense. On the upside, it would be pretty much the only way to go from 5D to 4D shaders while keeping control overhead (and the theoretical alu/tmu ratio) the same.

 

Actually, when one thinks about it, it should work pretty well for graphics workloads, where the wavefront size doesn't matter that much (compared to some GPGPU algorithms were you are basically tied to certain work group sizes because of LDS and stuff like that). All what changes is that the tile size of a wavefront (at least the natural one, the rasterizer are able to reorder it either way with a small penalty) would grow from 4x4 quads (8x8=64 pixels) to 5x4 quads (10x8=80 pixels).
Edit: Just as I read my own post, one of the current rasterizers with 16 pixel/clock would fill a wavefront of 80 pixels over 5 cycles instead of 4 now. Should be no problem.

I hoped AMD would overhaul the texture filtering a bit which appears to be L1 Tex cache bandwidth starved for trilinear and AF currently (that the bilinear rate is far above Fermi isn't that much of an advantage in quite some scenarios). Without a redesign of the TMUs and the Tex cache, slightly lowering the Alu/Tex-Ratio might have proven beneficial and maybe enough to use some more samples without impacting performance too much.

 

Looking at the TDP of Bart, we could guesstimate the specs of Cayman..
At 200 W TDP, there is space for 1920sp with the improved power efficiency.

 

Mao, i won't tell you again to stop it with the inter-forum/chinese leak superstar drama that we don't really care about. Next time you go on one of those tangents, I'll make sure we're free of them for quite a while - so please don't.

 

Even Dave? Sheesh, that's harsh.

 

If the removal of the T-unit compacts the VLIW structure area with 25%, that would mean (with linear relation) AMD could fit 2000 of the simpler ALUs in the same die space as Cypress' 4+1 configuration. That would put Cayman's SP count between 1920 and 2048, i.e. 30 or 32 SIMDs. Add to that the expected larger die (~385 sq.mm), to accomodate for the improved "uncore" functionality and etc.

 

Can't add SIMDs without adding TMUs.

What if the TMUs went on a diet, something that the patent documents I linked earlier vaguely hint at...