AMD: R7xx Speculation

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This is an internal bus. How do 512 pins come into this? :???:
You started talking about the ringbus after quoting this part of my post : "They would also have to engineer a chip to chip interconnect operating at very high frequencies ... "

So I assumed you meant they could simply use the ring bus at 500 MHz as an external bus.
 
You started talking about the ringbus after quoting this part of my post : "They would also have to engineer a chip to chip interconnect operating at very high frequencies ... "

So I assumed you meant they could simply use the ring bus at 500 MHz as an external bus.
Ah, OK. The text I posted was about the fourth in a chain of thoughts, so the first version was prompted by what you said but that linkage got ever more tenuous with re-thinking it.

I'm curious what the actual internal ring bus bandwidth needs to be in order to make the GPU work. Is the speed of the GDDR all that determines ring bus speed?

If you can build a link GPU<->memory that runs at 4GHz effective (GDDR5) then perhaps you can use additional links of the same type for GPU<->GPU communication. 8x faster implies only 64 data lines.

Right now I'm assuming that the two GPUs would be connected by a "branch", just like GPU and CPU are connected by a PCI Express branch that's routed off a dedicated ring stop.

Jawed
 
19250271zo9.jpg

I see something...
 
Very interesting.

Few possible scenarios just by looking at the cooling solutions:
- R700 uses two RV770 Pro chips for thermal management, RV770 XT runs really fast and needs that R600 slot cooler and RV770 has a TDP of ~100w;
- R700 uses two RV770 XT chips, RV770 XT's cooler is overkill and RV770 Pro is roughly the same as RV670 (TDP wise).
Maybe there is different rpm on the fans? While 4870x2 sound like a leaf blower the 4870 is nice and quiet? :)
 
From what I've seen here, this is my understanding of rough price points and performance, in order from lowest in performance to highest:

These are disregarding any 512MB/1GB variations... just the chip itself.

1) ATI HD4850 at ~$250
2) ATI HD4870 at ~$350
3) Nvidia GTX260 at ~$450
4) Nvidia GTX280 at ~$550+
5) ATI HD4850x2 at ~$500
6) ATI HD4870x2 at ~$550

7) Nvidia GTX260x2 ??? at ~$550+ (assuming 65nm, if possible)
8) Nvidia GTX280x2 ??? at ~$600+ (assuming 65nm, if possible)

We see Nvidia coming in the lead for the single cards, but this time (as different with the 38xx series) the x2 takes the lead significantly over Nvidia's single offerings.

What's particularly interesting is the CrossfireX ability of the new 48xx series. We'll be seeing true memory sharing and chip integration, which means an actual x2 card will look as if its just 1x. CrossfireX will still show 2 I believe, but the memory may still be shared? AND, its cheaper than the GTX280.

Make adjustments to my assumptions, as they are based off of incomplete reports from around the web.
 
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EDIT: Is it just me, or does the die footprint(s) seem larger on the R700 cooler compared to the RV770 XT/Pro cooler?

Maybe because R700 is optimize for shared 512bit memory controller between 2 GPU cores - and it has to be a bit bigger die to fit 512bit.


EDIT: AMD said before that R700 is not going to be same ordinary way as R680 was - slapping 2x RV670 on single PCB - Maybe R700 "R4870X2" has modified 2x RV770 GPU's.
 
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Indeed, integrated PCI E bridge?!
Hmm, looked like an absence of bridge chip on my crappy work monitor.
Looks like there is black heatsink there afterall on my home monitor with the help of the gamma slider :oops:
 
I'm probably just imagining things and it's hard to say without an actual analysis of the heatsinks, but I do echo Shtal that the actual chip footprint seems larger on the R700 than the RV770 pictures. But that could easily be an optical illusion.

FWIW whether that contact area for the PCI bridge chip is there or not doesn't really matter since the cooler is nearly identical to the R680 one so it doesnt mean there will or will not be a chip there in any certainty.
 
Provided this really is an R700 cooler, I think we can say goodbye to the shared memory & no-PCIe-bridge design rumours…
 
I'm probably just imagining things and it's hard to say without an actual analysis of the heatsinks, but I do echo Shtal that the actual chip footprint seems larger on the R700 than the RV770 pictures. But that could easily be an optical illusion.
Forget the R700/RV770XT cooler pictures wrt to die size - contact area of cooler oftentimes is significantly larger than the actual die size for a variety of reasons.

Taking a look at the supposed RV700 Pro cooler seconds that and also adds to that a (again: supposed) footprint of actual die size as it's been impressed into the TIM. :)
 
Of course, that assumes that building and integrating such an interconnect is:

a)Simple- there's no indication of this being the case

I think the ring bus (in their arch. for least 2 generations) is an indication of them working on this ahead of time. Not simple, but pretty much solved the internal arch. features. I don´t think the external part of the interconnect is more complex than the architectural requirements that are already solved.

b)Efficient- if you end up wasting a lot of trannies in single chip just to make em multi chip ready, what's the benefit

Do you have any estimate of the cost in % of die space to implement such an external bus? Me neither but I guess < 5%, in other words: not much.

c)A one time thing- namely you do the research once, and then can simply plug it in your chips going forward, with moderate adjustments-if you have to rework the implementation for each new generation, you're getting into more trouble than it's worth.

I am not sure at the moment, but I think I read somewhere that the ring bus and several other parts of the R6XX arch. are modular. The ring bus seems to be modular when it comes to adding ring stops.

Is this what you are referring to here?

It's not necessarily undoable, but as soon as you start looking at implementation details you start seeing that you're not gaining all that much from making a single big chip by taking the "proper" multi-chip route. I'd love to be wrong on this, but my hunch is that AFR will be with us for quite some time, with the multi-chip approach simply getting some tweaks, but nothing really paradigm shifting, like MfA was suggesting.

I will not say you are wrong, but at least in this post I only see over simplified assumptions with no facts or examples to back them.

How can you come to the conclusion that ¨you're not gaining all that much from making a single big chip by taking the "proper" multi-chip route¨?
 
Well I'd say that internal ring bus they've had in R600 and carried onto RV670 and like R7xx family has to serve *some* purpose unless ATI likes to waste resources. As to how it will actually function though, I guess we have to wait and see.

I'm still amazed this card is supposedly 3 weeks away and we haven't even had a leaked die picture that's legitimate - while Nvidia has had pretty much everything leaked already. Very uncharacteristic.
 
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