AMD: Pirate Islands (R* 3** series) Speculation/Rumor Thread

Using this picture:

AMD-Fiji-GPU-High-Resolution-Shot.jpg


The smallest I can make Fiji is 21.8 x 25.7 = 560mm².

One thing I've realised about the interposer, that I think we've all missed, is that the reticle limit doesn't constrain the size of the interposer. It solely constrains the area of the interposer used for interconnects.

Hence I believe we can see in this picture how a "copper" coloured area is substantially smaller than the "green" area of the interposer. In fact it appears that the etched area within the interposer does not extend for the full height of Fiji, nor does it extend to the full width of the HBM modules :!:

So, that's how you get an interposer that's substantially larger than the reticle limit :p
 
Jawed said:
One thing I've realised about the interposer, that I think we've all missed, is that the reticle limit doesn't constrain the size of the interposer. It solely constrains the area of the interposer used for interconnects.
...

So, that's how you get an interposer that's substantially larger than the reticle limit :p
Click to expand...

Erm, not being funny but someone pointed that out several weeks or months ago. I think it was here (3d.\*)? but could have been RWT or AT.
 
Jawed said:
One thing I've realised about the interposer, that I think we've all missed, is that the reticle limit doesn't constrain the size of the interposer. It solely constrains the area of the interposer used for interconnects.

Hence I believe we can see in this picture how a "copper" coloured area is substantially smaller than the "green" area of the interposer. In fact it appears that the etched area within the interposer does not extend for the full height of Fiji, nor does it extend to the full width of the HBM modules :!:

So, that's how you get an interposer that's substantially larger than the reticle limit :p
Click to expand...

CBLvU08.jpg


Probably very conservative guess on my side.
 
Jawed said:
Using this picture:

The smallest I can make Fiji is 21.8 x 25.7 = 560mm².

One thing I've realised about the interposer, that I think we've all missed, is that the reticle limit doesn't constrain the size of the interposer. It solely constrains the area of the interposer used for interconnects.

Hence I believe we can see in this picture how a "copper" coloured area is substantially smaller than the "green" area of the interposer. In fact it appears that the etched area within the interposer does not extend for the full height of Fiji, nor does it extend to the full width of the HBM modules :!:

So, that's how you get an interposer that's substantially larger than the reticle limit :p
Click to expand...

It would seem to be both the area for interconnect and power/ground.
In the case of the HBM base die, there is a strip for the testing pads that is ubump depopulated, which may correspond to the margin the stacks have in the photo. The PHY and power/ground areas probably lie within the etched area.

Fiji in the non-glare region does not seem have as much free margin as the HBM stacks do.
The dead space would probably be kept small, since it impacts the number of candidate interposer dies and would not affect the processing steps needed for the etched areas. Possibly for mechanical reasons, it may not drop to zero.
 
CarstenS said:
WRT to why AMD did not yet release a „full Tonga“: Until a few weeks back, R9 280-cards were priced VERY compellingly here in germany, probably clearing stock from the channel. That might have played a role.
Click to expand...
The number of 280 cards in the channel for sale has been absurd. For a card that was supposed to be phased out 9 months ago it has been incredibly tenacious. I can't imagine AMD kept producing Tahiti once they had Tonga, which means they must have had a huge stockpile of Tahiti chips lying around.

CarstenS said:
Apparently there were two: One overview and one "architecture" - the last one probably only given to techday attendees?

I've included the architecture-labelled one here:
http://www.pcgameshardware.de/CPU-H...-HSA-drei-Modelle-von-15-bis-35-Watt-1160641/


Nope, it was sent via PR agency to probably all Carrizo techday attendees. I didn't know until today that other press only got the overview.
Click to expand...
Confirming that we had the Architecture deck from Tech Day as well.
 
Last edited:
nutball said:
Erm, not being funny but someone pointed that out several weeks or months ago. I think it was here (3d.\*)? but could have been RWT or AT.
Click to expand...
Yep, could have been months ago when I was in ignore mode.

But you and everyone else who "knew" that have had weeks to say so with respect to my multiple postings all explicitly on the topic of maximum interposer size. So I guess you were being funny, withholding your insight all these weeks :LOL:
 
Most of the papers and discussions about maximum interposer size did focus on the area available for power/ground and interconnect. The probable assumption was that most of the chips being used would have their footprint primarily determined by their microbump footprint. Some hand-waving may have been involved in excluding the margin needed to give enough space for the epoxy and other materials to bond.

For the GPU, it seems to be close enough. The debumped test pad area for the that particular base die may have been something of a product-specific quirk that only those working with an design implementing it would be aware of. It does seem like a worthwhile optimization to make for an interposer satellite die, but one that might not always be there.

Does it seem to buy the GPU 1-2mm?

Maybe in theory, the rumor about a dual-linked configuration could be implemented with HBM stacks on another interposer that could extend out over a wider dead zone on the main interposer. The price picture for that particular workaround seems daunting.
 
The HBM base die ballout for PHY appears to be about 1.6mm in the shortest dimension. But I think much of that apparent saving can be discounted as the wires in the interposer appear to be configured to enter the PHY ballout from all four sides. So 0.5mm or so per HBM?

I suppose the wiring density within the interposer is a question of layer count. With more layers it would be possible to enter PHY ballout from only 3 sides, thus gaining about 1mm per HBM module. So with HBM arrayed down two sides of a GPU, there'd be 3mm best case gain from this optimisation.

But are more layers an option? Most of the examples of interposers seem to have 4 layers.
 
On review, it looks like the pad area that was depopulated is itself within a region of other bumps.
The white space shown for the KGSD package bottom view has a margin that looks to be rather close to what is hanging off the edge of the usable interposer area.

I am not sure that upping the layer count is going to help. The gridded area for both the PHY, power/ground, and the test port for the bottom of the stack is more than half the 5.48 dimension, and only one side's margin is going to be available.
 
When you are familiar with the work of true artists, Picasso, Mondrian, Paul Klee, you probably have noticed that they evolved from painting realistic tableaus to ever more abstract representations, stripping away the unnecessary details until only the bare and true essentials are remained in their rawest form.

This supreme form of reduction doesn't only exist in the world of painting, it also manifests itself in the more mundane world of journalism. The following article illustrates this very well: http://semiaccurate.com/2015/06/03/amd-shows-wont-say-fiji/
The artist in question hasn't quite reached the pinnacle of his abilities, but it shouldn't surprise anyone if, a couple of years from now, all this articles will be reduced to just 4 words: "I told you so."
 
gamervivek said:
Apparently news going around that GCN won't support dx12_1, of course neither would the xbone chip.
Click to expand...
Current GCN versions don't, Fiji and possibly the rest of Radeon 300 -series might.
(Considering apparently all GCN 1.0 chips except Tahiti got already updated to 1.1 ages ago on the compute front without anyone noticing it, I wouldn't be surprised about anything)
 
Hallo, guys!

First of all, I would like to tell you that I am back after some quite long absence.

Unfortunately, I see some quite strong confusing and negative (in general and against AMD) things circling around, probably coming from the nvidia pr trying to hurt AMD.

gamervivek said:
Apparently news going around that GCN won't support dx12_1, of course neither would the xbone chip.
Click to expand...

AMD Confirms GCN Cards Don’t Feature Full DirectX 12 Support – Feature Level 11_1 on GCN 1.0, Feature Level 12_0 on GCN 1.1/1.2

Read more: http://wccftech.com/amd-confirms-gc...-10-feature-level-120-gcn-1112/#ixzz3cDXM9ujS

Nonsense to which the response is this:

Roy@AMD @amd_roy
@Ramzinho @Thracks zero, absolutely zero. AMD supports DX12. Period.

Anyways - how many times in the past did we see how nvidia didn't support some versions of DX (DX 10.1, DX 11.2, DX 11.3, etc)?

In this case the feature level doesn't even mean that those support DX12dot1 but DX12 feature level 12_1...

AMD DirectX 12 GCN Support:

Model Graphics Core Next Architecture DirectX
Radeon HD 7000 series GCN 1.0 DX12, feature level 11_1
Radeon HD 7790 GCN 1.1 DX12, feature level 12_0
Radeon R7 260 (X) GCN 1.1 DX12, feature level 12_0
Radeon R9 270 (X) GCN 1.0 DX12, feature level 11_1
Radeon R9 280 (X) GCN 1.0 DX12, feature level 11_1
Radeon R9 285 GCN 1.2 DX12, feature level 12_0
Radeon R9 290 (X) GCN 1.1 DX12, feature level 12_0

NVIDIA Direct X 12 GPU Support:

Model DirectX
GeForce 900 Series (Maxwell 2.0) DX12, feature level 12_1
GeForce 700 Series (Maxwell 1.0) DX12, feature level 11_0
Partial feature level 11_1 support
GeForce 700 Series (Kepler) DX12, feature level 11_0
Partial feature level 11_1 support
GeForce 600 Series (Kepler) DX12, feature level 11_0
Partial feature level 11_1 support
GeForce 500 Series (Fermi) DX12, feature level 11_0
Partial feature level 11_1 support
GeForce 400 Series (Fermi) DX12, feature level 11_0
Partial feature level 11_1 support

Read more: http://wccftech.com/amd-confirms-gc...-10-feature-level-120-gcn-1112/#ixzz3cDaSCiXA
 
So apparently Tonga does have a 384bit bus: http://wccftech.com/amd-tonga-gpu-d...controller-fiji-die-size-approximated-560mm2/

A "fully" enabled Tonga would hit 14%+ above a standard 285 with the same clock speeds, assuming performance isn't bound by bandwidth in which case it would do even better. Placing it squarely between a Nvidia 960 and 970 in terms of performance. Considering there's a $125 gap between those two it seems like a nice place to be.
 
Well yeah wccf finally seems to have got the memo, at least they credit their source which is of course two pages before in this thread. I should've linked to the post itself.
 
I thought you need to actually have full feature level support to use the features of that feature level?
 
Honestly I don't see why almost anyone should care about what level of DX/Shader model the new cards support. There really isn't a whole lot of useful features anymore, at least compared to what their used to be with the big updates. "DX12" is more interesting because of explicit control, which is backwards compatible, than any particular hardware feature or even the whole set of hardware features.
 
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