AMD: Pirate Islands (R* 3** series) Speculation/Rumor Thread

HBM is actually supposed to save a good bit of power, about 50% of the power consumed by GDDR5 while providing about twice the bandwidth according to some slides, if I remember correctly. Presumably this includes the power drawn by the memory chips, the bus and the PHY on the GPU.

And how much real power is actually saved?

Isn't most of the power of a video card being used by the GPU and the VRMs with the memory taking maybe 10-15 watts?

If so then the savings would only be 5 - 7.5 watts which is not very much on a 300 watt card.
 
And how much real power is actually saved?

Isn't most of the power of a video card being used by the GPU and the VRMs with the memory taking maybe 10-15 watts?

If so then the savings would only be 5 - 7.5 watts which is not very much on a 300 watt card.

I aggree with that, the ratio of vram power consumption is small ( 15watts maximum for a 4GB 7Ghz area of GDDR5 ) .. but this too mean thoses power consumption can be allocated to the gpu core itself .

This said, i have no idea what imply HBM, in the core itself, internally this should provide some big change.. a 4096bit bus will ask naturally for a big change on the second level cache .... the data traffic from the SM through this cache will be a lot impacted by it, and the overal gain in power consumption too...

its not only the question of the gain of HBM memory or stacked memory gain, it should / will modify deeply all the architecture.
 
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Hight frequency memory controller are hard to do, while in hbm the memory controller is on the memory itself so the gpu must only connect to it
 
Hight frequency memory controller are hard to do, while in hbm the memory controller is on the memory itself so the gpu must only connect to it
The high frequency part in a GDDR5 system is just the external data link between otherwise much lower frequency logic on both sides. In HBM, there shouldn't be any high frequency logic. It's not moved inside the HBM die, it's not there at all.
 
This said, i have no idea what imply HBM, in the core itself, internally this should provide some big change.. a 4096bit bus will ask naturally for a big change on the second level cache .... the data traffic from the SM through this cache will be a lot impacted by it, and the overal gain in power consumption too...
No, it shouldn't be impacted much at all.

There is no 4096 bit bus. There are 4 1024 bit busses, one for each stack of dies.
And it has been a while since I've last looked at those Hynix slides, but I believe that inside each stack, the bus is again logically split in 2. So that's only 512 bits or an access granularity on 64 bytes. That's the same or only double of DDR3. IOW you don't need to change much at all.

The way I look at HBM is that it's essentially the same a GDDR5 with the external data bus clocked down but demultiplexed with a larger factor so you end up with a net gain. And with lower power because you lose the high frequency PHYs.
 
Isn't the memory controller in hbm a distinct die in the 3d stack? Or I confuse it with hmc?
That's the logic that controls DRAM internal timing, self-refresh etc. No different than what's already present on traditional DRAMs.
 
And how much real power is actually saved?

Isn't most of the power of a video card being used by the GPU and the VRMs with the memory taking maybe 10-15 watts?

If so then the savings would only be 5 - 7.5 watts which is not very much on a 300 watt card.

Ummm... pretty sure it is quite a bit more than that. Plus the memory controllers/interface are definitely quite power consuming.
http://mediasite.colostate.edu/Medi...e9c8cf474a8f887157581c458a1d&playFrom=1020000

http://www.dongpingzhang.com/wordpress/wp-content/uploads/2012/04/TOP-PIM-HPDC-paper.pdf

Edit- Just want to mention, since I haven't caught it before. I believe the chip he is talking about on the first link, is GM204, at the ~20min mark.
 
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135% performance, 161% power consumption compared to the 980, 290x is 89% of the performance at 157% of the power so as has already been said about 1.5x better perf/w which is a good gain. Still ~84% of the perf/w of the 980 though. Obviously we don't know if they're real so a salt shaker will be required.
 
Looks like it'll need a water solution again to be competitive.
 
Looks like it'll need a water solution again to be competitive.

There's no problem with more capable air cooler as provided by MSI, Asus and other brands. ( dual, triple fans )

Their hybrid water solution, was used on the 295x2 ( dual gpu ). I really doubt you will "need" one for a 290x or a gpu with similar TDP .. If they do it for the reference card, this will be a design choice, instead of an necessity.
 
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Looks like it'll need a water solution again to be competitive.
290X GPU cards are cooled just fine with air, so no problem on that front. Water just complicates things, like how do you run such a setup in crossfire? It'll be difficult to find room to fit the second radiator.
 
If they do it for the reference card, this will be a design choice, instead of an necessity.
...it is a necessity - to not have bad reviews just for the noise (one would think it doesnt matter in reference design but it is, according to reviewers..) and -maybe- put slightly higher default clock?
 
...it is a necessity - to not have bad reviews just for the noise (one would think it doesnt matter in reference design but it is, according to reviewers..) and -maybe- put slightly higher default clock?

Many custom 290X cards, even slightly overclocked ones are pretty quiet. There's really nothing stopping AMD from adopting a similar cooler as a reference design.

But I suppose a hybrid cooler could be very quiet while providing a decent amount of overclocking headroom, which enthusiasts might appreciate.
 
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