That 384-bit bus on Tonga was just a dumb mistake.... (http://www.pcper.com/news/Graphics-...a-384-bit-Memory-Bus-Not-Enabled-Any-Products)
One wonders how many millions were left on the table right there...
Are the L2 caches tied to the memory controller?
The reason? The company never found the right price/performance combination.
One wonders how many millions were left on the table right there...
Are the L2 caches tied to the memory controller?