Playstation 5 [PS5] [Release November 12 2020]

Yeah...
Both have their own unique attributes that's not exactly replicated in the normal PC GPU space, so it's rough keeping all the numbers straight.

It is fairly close enough. At least until we have solid information, if ever. It's a bit curious that so much info is still kept as secret even at a point in time when neither side can make adjustments. :LOL:
 
ThePissartist said:
Ah okay, that makes more sense. So it's 6.7 Vs 7.5

It's close enough that the difference could easily be Tempest and larger space for IO.
Click to expand...
What should also be taken into account, beside extra CU for Tempest, is the fact that increase in CU per mm2 for XSX is duo to fact that :
  • PS5 has 256bit bus for 40CUs, while XSX has 320bit bus for 56CUs (40% increase in CU count, 25% increase in PHY)
  • PS5 has 2 shader engines for 40CUs, while Series X also has 2 (albeit with 5MB of L2 v 4MB in PS5 I assume)
So basically, 40% increase in CU count does not follow 40% increase in entire SOC, nor in fact does it follow 40% increase in GPU portion itself.
 
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BRiT said:
Yeah...
Both have their own unique attributes that's not exactly replicated in the normal PC GPU space, so it's rough keeping all the numbers straight.

It is fairly close enough. At least until we have solid information, if ever. It's a bit curious that so much info is still kept as secret even at a point in time when neither side can make adjustments. :LOL:
Click to expand...
I said 36CUs clocked at 2.0GHz at 399$ would be perfection for SOC back in late 2019 and the one I would design if I was Mark Cerny in my dream :D

What we got is a little more then that + lots of other goodies. Because of the fact that XSX GPU was not scaled up linearly with CU count, it wouldn't be surprising to see PS5 being less then 18% of "theoretical" deficit minimum (provided it doesn't downclock too much and performance scales with those clocks, but it could also be the case there won't be linear increase duo to cache misses).

Now obviously if there are any features missing in either which make some things cheaper to render then it all goes a bit out of the windows, but I am happy how things panned out for both.
 
AbsoluteBeginner said:
What should also be taken into account, beside extra CU for Tempest, is the fact that increase in CU per mm2 for XSX is duo to fact that :
  • PS5 has 256bit bus for 40CUs, while XSX has 320bit bus for 56CUs (40% increase in CU count, 25% increase in PHY)
  • PS5 has 2 shader engines for 40CUs, while Series X also has 2 (albeit with 5MB of L3 v 4MB in PS5 I assume)
So basically, 40% increase in CU count does not follow 40% increase in entire SOC, nor in fact does it follow 40% increase in GPU portion itself.
Click to expand...

I'm waiting for @iroboto's geometry lesson for final confirmation.
 
ThePissartist said:
I'm waiting for @iroboto's geometry lesson for final confirmation.
Click to expand...
lol
you guys worked it out well enough.
Basically if you go by 360mm^2 vs about 305/315mm^2. PS5 is about 1/7 smaller.
The blue line is where a hypothetical PS5 would stop in terms of area (~305mm2)
I've indicated the CUs in red boxes (admittedly, I screwed up and went too narrow on the 8CU part, whoops). The remaining of the GPU (top section) are the fixed function units.
GDDR6 controllers probably take up as much area as those IO under the blue line.
So you've got very little room to spare for something.

If you use the L3 on the Zen 2 as a guide, that's a lot of silicon there spent for cache, but it's actually a very small amount - someone mentioned a few MB only. Not sure if you have enough for even that. Maybe squeeze an extra 8MB of cache - maybe 16MB according to the recent revision on how small infinity cache is?

I still don't know what infinity cache does.

7CCcXxj.png
 
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iroboto said:
lol
you guys worked it out well enough.
Basically if you go by 360mm^2 vs about 305/315mm^2. PS5 is about 1/7 smaller.
The blue line is where a hypothetical PS5 would stop in terms of area (~305mm2)
I've indicated the CUs in red boxes (admittedly, I screwed up and went too narrow on the 8CU part, whoops). The remaining of the GPU (top section) are the fixed function units.
GDDR6 controllers probably take up as much area as those IO under the blue line.
So you've got very little room to spare for something.

If you use the L3 on the Zen 2 as a guide, that's a lot of silicon there spent for cache, but it's actually a very small amount - someone mentioned a few MB only. Not sure if you have enough for even that. Maybe squeeze an extra 8MB of cache?

7CCcXxj.png
Click to expand...
All would depend on the real size. Is not the same 305 than 315. Infinity cache seems to be near 1,5 times denser than Zen L3, so 32MB would be near 20mm2.

And we still have that SRAM in the IO block:

https://imgur.com/35jGMak
 
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