TSMC's 5nm is fairly likely to be better than Intel's 10nm, though, at least in power-efficiency around 4.5GHz.
On the chiplet, the IF phy is right smack in the middle between the two CCX clusters (flanked by the L3 arrays).
Looking at the I/O chip, the Rx and Tx pads of the IF phy does seem to be symmetrical in size, so no evidence of half-width upstream link there, unless the upstream link is half wired in the substrate package.
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Full ISA throughput/latency dump for Zen2: http://users.atw.hu/instlatx64/AuthenticAMD0870F10_K17_Matisse_InstLatX64.txt
Slight reduction of FPDIV op's throughput (singles and doubles) compared to the previous generation.
Vector gathering still takes more cycles compared to Haswell, but faster than Zen1.
Slight reduction of FPDIV op's throughput (singles and doubles) compared to the previous generation.
Vector gathering still takes more cycles compared to Haswell, but faster than Zen1.
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Asus publishes X470 and B450 PCIe Gen 4 compatibility chart
https://hexus.net/tech/news/mainboard/132656-asus-publishes-x470-b450-pcie-gen-4-compatibility-chart/
I agree, Asus seems to like to throw everything and the kitchen sink in their ROG stuff regardless of cost 'cause they just jack the price up and pass it along to the consumer, I don't get why they don't have it either.Seems odd that the ROG boards are the ones which DON'T support PCI-e Gen 4
3700 < 3900, DUH!
(Just teasing, I have no clue what I'm talking about but it sounded perfectly sarcastic so I couldn't resist. My apologies.
)Seems odd that the ROG boards are the ones which DON'T support PCI-e Gen 4
Doesn't the ROG boards reserve 4 lanes from the CPU to the chipset or something?
The 3700X seems to be locked at 4.0GHz here. Presumably, the 3900X isn't, so since the results are in ns and not cycles, it could simply be due to the clock speed difference.
The IO chiplet's size is very near the estimated non-core area of a Summit Ridge Zen, which leaves little leeway for a die still at 12/14nm. The Zen 2 CPU chiplet is smaller, but the L3 looks to be the dominant consumer of area on that chip and its area would be noticeable on the IO die. Since the IO die can support 2 CPU chiplets, having the L3 for two would be very noticeable.
I didn't see any major asymmetry in those arrays either, although I'm curious if the area the IO die devotes to those presumed IFOP links is similar to what they were on Summit Ridge. I recall it being stated that the links are double in width, but they seem bigger or at least the PHY appear more noticeable than before.
I'm not seeing a visually similar area on the CPU die, unless it's lost in the glare on one side. Perhaps the PHY chosen for the chiplets differ so much because of the node difference. Although if perhaps the CPU-side PHY sacrificed drive strength for area or somehow didn't match well with the chunky PHY on the IO die, running the data path that the CPU side needs to drive at a slower speed could save power or allow for better compatibility.
Hi-res chiplet shot:
Is it me, or the L1i cache array is way too large for 32KB? The L1d cache looks fine, though.
Another thing, the two FMA/SIMD pipes are now clearly distinguishable. Looks like AMD made a new layout for that part of the architecture, not just extend the data paths to 256-bit.
Is it me, or the L1i cache array is way too large for 32KB? The L1d cache looks fine, though.
Another thing, the two FMA/SIMD pipes are now clearly distinguishable. Looks like AMD made a new layout for that part of the architecture, not just extend the data paths to 256-bit.
All the boards do, it's the connection AMD uses between SoC and FCH or whatever the latest acronym for their "chipset" is
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