Perhaps the section labelled L1 I$ for Zen included the L1 and uop cache. For both cores, maybe the uop cache is the narrow rectangular bank that juts out from the rest of the L1. For the Zen 2 shot, the top left core might have it run along the entire upper side instead of yielding space to the L1.
For Zen 2, this section is bigger. At the same time, the bottom side has something jutting out a little as well from the L1 block, unlike in Zen 1. However in Zen 1 there are other rectangular regions that are either predictors or a thin rectangular region that was in a nebulous decode block. Perhaps some of the lower parts of that array aren't L1 I$ either?
It might be clearer with a more detailed die shot that actually etches down into the silicon rather than using infrared light. The notes for the shot on Flickr indicate the corner of the Zen 2 chiplet was cracked anyway.
There does seem to be some PHY in the right side of the mid-line of the chiplet, with some blocks that have some resemblance to the IO die's presumed IF PHY. They might be smaller on the CPU die, and I'm not sure what the bright area around it might be. There is a lesser number of such blocks on the left side. From the initial view of this layer of the chiplet, perhaps the IO die is equipped with more IFOP lanes than the current Zen 2 chiplets have.
I'll be curious if profiling of Zen 2's 256-bit operations shows a warmup period similar to what Intel's cores have had since Sandy Bridge. Before, Zen's cracking of operations meant the always-active 128-bit units didn't need to be woken up. The new pipeline might be gating off the unused high side, which might introduce the need for warmup.
