AMD Ryzen CPU Reviews and Previews (3000 series)

Yeah but not all XXnm are equals. The first 10nm by Intel was very ambitious, being better in some aspect that today 7nm by tsmc. It didn't work out, but "5" isnt always better than "7".
 
Yeah but not all XXnm are equals. The first 10nm by Intel was very ambitious, being better in some aspect that today 7nm by tsmc. It didn't work out, but "5" isnt always better than "7".

TSMC's 5nm is fairly likely to be better than Intel's 10nm, though, at least in power-efficiency around 4.5GHz.
 
The chiplet layout is very compact and "skinny" regarding I/O. AMD made a wise choice to separate all the PHY junk away from the high-speed CPU design.
 
Last edited:
How much space is taken by IF?
The IO chiplet is so big that until some point I was sure that all the L3 cache was there.
 
How much space is taken by IF?
On the chiplet, the IF phy is right smack in the middle between the two CCX clusters (flanked by the L3 arrays).
Looking at the I/O chip, the Rx and Tx pads of the IF phy does seem to be symmetrical in size, so no evidence of half-width upstream link there, unless the upstream link is half wired in the substrate package.
 
Last edited:
Asus publishes X470 and B450 PCIe Gen 4 compatibility chart
Hallock stated that "Pre-X570 boards will not support PCIe Gen 4," despite some tech news and social media chatter he had observed during Computex week. This included screenshots of updated BIOS UIs from AMD 300 and 400 series chipset motherboards which allowed the user to toggle various PCIe slot generation options, including PCIe Gen 4. Hallock went on to say that such options were present in non-final BIOS updates and would be removed going forward.

Now it looks like some manufacturers, like Asus, disagree with AMD's idea that generational hardware support should be a simple yes or no, across chipsets. The AMD Ryzen 3000 processors offer 16 PCIe 4 lanes for graphics cards and four more lanes for M.2 NVMe SSDs, and it seems that these are partly usable with a new BIOS applied to various Asus motherboards with the X470 and B450 chipset.
...
Some testing of the above Asus motherboards has already been undertaken. ComputerBase reports that Chinese site MyDrivers tested a PCIe Gen 4 SSD on the TUF B450M-PRO Gaming. This setup reportedly achieved around 5.0GB/s reading and 4.2GB/s writing performance, similar to what you might expect for an X570 motherboard with PCIe Gen 4 M.2 SSD combo.
https://hexus.net/tech/news/mainboard/132656-asus-publishes-x470-b450-pcie-gen-4-compatibility-chart/


 
Seems odd that the ROG boards are the ones which DON'T support PCI-e Gen 4 :oops:
I agree, Asus seems to like to throw everything and the kitchen sink in their ROG stuff regardless of cost 'cause they just jack the price up and pass it along to the consumer, I don't get why they don't have it either.
 
How much space is taken by IF?
The IO chiplet is so big that until some point I was sure that all the L3 cache was there.
The IO chiplet's size is very near the estimated non-core area of a Summit Ridge Zen, which leaves little leeway for a die still at 12/14nm. The Zen 2 CPU chiplet is smaller, but the L3 looks to be the dominant consumer of area on that chip and its area would be noticeable on the IO die. Since the IO die can support 2 CPU chiplets, having the L3 for two would be very noticeable.

On the chiplet, the IF phy is right smack in the middle between the two CCX clusters (flanked by the L3 arrays).
Looking at the I/O chip, the Rx and Tx pads of the IF phy does seem to be symmetrical in size, so no evidence of half-width upstream link there, unless the upstream link is half wired in the substrate package.

I didn't see any major asymmetry in those arrays either, although I'm curious if the area the IO die devotes to those presumed IFOP links is similar to what they were on Summit Ridge. I recall it being stated that the links are double in width, but they seem bigger or at least the PHY appear more noticeable than before.
I'm not seeing a visually similar area on the CPU die, unless it's lost in the glare on one side. Perhaps the PHY chosen for the chiplets differ so much because of the node difference. Although if perhaps the CPU-side PHY sacrificed drive strength for area or somehow didn't match well with the chunky PHY on the IO die, running the data path that the CPU side needs to drive at a slower speed could save power or allow for better compatibility.
 
Doesn't the ROG boards reserve 4 lanes from the CPU to the chipset or something?
All the boards do, it's the connection AMD uses between SoC and FCH or whatever the latest acronym for their "chipset" is
 
Back
Top