Thats interesting actually...So 4core ryzen will have a huge jump in performance?
ProspectorPete
Regular
Remember the "OMG RX480 is break PCE-I spec, power draw 150W TOO HIGH, my mobo is fried, it CANNOT BE FIXED!!11"?
I really want to see some reviewers playing with SMT and affinity. I'd love to see gaming results with process affinity limited to cores 0-3 and SMT on. Might be a great way to eek some performance out of current games which may be causing possible CCX hopping and hitting that latency.
Early days, still a lot of discovery to go. If MS ends up coming out with OS-level patches like with Bulldozer.... why wasn't this found and done months ago by AMD ready for launch?
Early days, still a lot of discovery to go. If MS ends up coming out with OS-level patches like with Bulldozer.... why wasn't this found and done months ago by AMD ready for launch?
hoom
Veteran
Imagine if at the start of this thread someone seriously suggested that the 1st iteration of Zen would be right up there with the latest Intel Expensive Edition on a lot of benchmarks, beating it in more than a few & about even in power while doing it:
I hoped that AMD could at least be in the ball-park so that buying AMD CPU wouldn't make people laugh at you, maybe beat a couple of gens old Intel stuff clock for clock. Hoped but didn't particularly believe it would happen
Note that Aida64 apparently haven't had a chance to update -> their cache numbers are wrong.
Also ran into this via Reddit
Might have thought they'd mention Jim Keller there, but maybe understandable since 'It was all because of this guy who doesn't work for us anymore' wouldn't be the greatest look...
Any sign of comment from him now that its launched?
Also anyone seen any detail around why he left other than 'Set stuff in order & on the right path so skipped the boring bit'?
ISA performance dump: http://users.atw.hu/instlatx64/AuthenticAMD0800F00_K17_Zen_InstLatX64.txt
hoom
Veteran
Interesting, can be fixed with BIOS update?
https://www.reddit.com/r/Amd/comments/5x54ww/my_theory_on_why_ryzen_does_not_perform_in_games/
https://www.reddit.com/r/Amd/comments/5x54ww/my_theory_on_why_ryzen_does_not_perform_in_games/
I think the question might be can AMD do that?
Per the voltage/clock analysis in the Anandtech link, single-core XFR (unsustainable, meager clock increase) to 4.1 is operating in a voltage range that is potentially damaging if sustained.
I've seen signs and discussion of thermal density issues increasing for the more compact form factors and its influence on why the desktop space has lagged mobile in getting the latest Intel cores. One trend, which I may have not noticed analysis for in the client space is the increasing impact of the fragility of modern processes on how much you can go "throw some TDP at this and get X MHz".
For a long time, it was generalized that the transistor budget was growing faster than TDP was scaling, leading to thermal limits that could be pushed if you wanted. Power density, to a certain extent, could be pushed if you went with more expensive cooling, although hot-spot issues may leave only so much margin with any mere mortal thermal solution.
However, enthusiasts have been complaining that they aren't getting to play with voltages anymore, with the response that they voltages they want are damaging.
Sufficient or excess cooling is equivalent to having TDP to spare. However, the ability for any single subsection of the die to receive or sustain the voltages and temperatures locally appears to have become noticeably different than saying that the cooler and board VRM are good enough. It was the case in the past that a core or few cores could reasonably be driven to hog all the TDP, but now I'm wondering exactly when it became noticeably separate for consumer parts.
For both, the definition has been pretty consistent for some time. I think it might not have been that different since perhaps the 90nm or 65nm generations, basically when either one hit the point where power consumption became crippling to future scaling and reliability.
It's how much power a thermal solution can be expected to dissipate in a thermally significant period of time, while the chip is running some set of representative software. They really cannot fudge this since it is concerning whether the chip burns itself out, although with modern DVFS and active sensors they can get much closer to the edge without engaging in the old debates over "representative loads". Now, the chips to a significant degree just know if they are on the edge, and can even weight the thermal capacity of the cooler to determine when exactly they can push the bounds of "thermally significant" in order to spike above it.
That hasn't been true for some time, and Intel likely broke from that first. AMD followed perhaps a little later, once it was able to get more than rudimentary power/thermal monitoring.
Not just TDP, since this seems to hit AVX clocks in some products if one core so much as sees one AVX2 instruction, which cannot reasonably overwhelm a cooler. This might go to power delivery/dissipation for specific parts of the chip rather than a global measure of the cooling solution.
It seems reasonable to count on GF's process being inferior, but absent that Zen's designers specifically noted that they've done things like use low-leakage and high-density cells for most of Zen. That means they've tuned the implementation with slower cells in areas that they reason won't need the significant area and leakage penalties of the cells that have half the linear delay--which holds true as long as the CPU is in some specified clock range. Pushing those efficient cells beyond that requires boosting the current enough to wreck power efficiency, or it takes them to the point of risking rapid physical degradation.
A Zen that can go faster would need to physically uprate its cells, accept larger area consumption and power consumption, and probably require a revamping of the power delivery of the chip and CCX, which appear to have limited headroom. "Balance" means not having a lot of slack outside of the target parameters.
Perhaps Zen's designers were given the philosophy of striving for 100% of the 90% of what can be done, and pare back anything that goes further.
256-bit AVX2 not really applying to more than 10% of the market Zen can hit? Don't do it.
Clocking to 4.2+ GHz when fewer than 10% of the products Zen can get to will ever get near that? Don't make a core that can do it.
Linux benchs thats pretty pretty good.
http://www.phoronix.com/scan.php?page=article&item=ryzen-1800x-linux&num=4
https://www.servethehome.com/amd-ryzen-7-1700x-linux-benchmarks/
http://www.phoronix.com/scan.php?page=article&item=ryzen-1800x-linux&num=4
https://www.servethehome.com/amd-ryzen-7-1700x-linux-benchmarks/
What would the test be to isolate this bandwidth? The auto-translation of the discussion is a little rough for me, was this measured or disclosed by AMD? In order to profile this, the lines in the other CCX would need to be dirty, otherwise they wouldn't respond (shared does not respond in MOESI). Perhaps this is subject to some kind of mandatory write-back of dirty data if leaving the visibility of a CCX, putting a ceiling on bandwidth+overhead?
Apparently, they got the word directly from AMD.
It seems like that. After the CCX arrangement was revealed, I mused that it looked like the organization was tailored for an easy match for a server hosting a bunch of VM allocations. That kind of workload can scale readily with this hardware, and also doesn't have the hard RAS requirements or hardware investment on the part of AMD.
That number is also half the measured the bandwidth of Ryzen's dual-channel memory controller.
The scheme seems to require that the same number of cores be off in both CCXs. I've seen this attributed to the needs of the synchronization methods of the data fabric.
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