NV got DS2 contract according to BSN
- Thread starter TEXAN*
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well, that still means nothing. not to mention tegra2 as we know it would hardly fit a pocketable handheld, let alone one by nintendo.
nVidia made a dev platform that has the needed interfaces for all the targeted segments. No doubt it's bigger than it could be :smile: I've seen many much larger devkits with less functionality.
Based on which metrics, though?
I posted the link as a good SoC size reference. i'm not implying anything else here. Tegra250 is one massive chip, no wonder it's being pitched at tablets/MIDs.
Or rather, it shouldn't mean anything, but a lot of people have been assuming that a standard Tegra 2 is what Nintendo bought.
Anyway, even if it's just "Gamecube level", it's not like Wii is much more than "Gamecube Ultra."
I'm going to parrot everyone else and say I don't really understand what the dev board size has to do with anything, isn't the chip itself even on a grid array adapter? Sure doesn't look very large to me.
Xmas said:
Mainly a rough assessment of:
CPU: clock for clock Gecko might offer a bit more, and if Tegra 2 doesn't have NEON then it has SIMD on it as well, but it's 2x1GHz vs 1x729MHz so it's hard not to give it to Tegra 2.
GPU: Fillrate seems similar, Tegra is much more programmable. Memory bandwidth might be a much bigger bottleneck on Tegra though.
Of course there'll be more hardware for various things and platforms with the chip will probably tend to have much more memory.
I don't really want to call it a clear winner but it's at least in the same neighborhood, I think. I guess I just wanted to call Tegra 2 "Wii level."
Tegra2 should get in the neighborhood of 1.2Gpix/sec with 50% z-culling, 480Mpix/sec drawn/shaded. You also get 5x CSAA for "free" (~10% hit). The Wii at most has to fill 640x480p @ 60hz, arguably handheld displays are higher resolution and the same framerate. To top it off you've got arbitrary length floating-point shaders and all kinds of goodies (like affine-transformed point sprites) on Tegra, so it should be able to beat the Wii on all fronts.
Agreed, but that's those people's own problem. The 'off-the-shelf-ness' prospects of this development are slim, to say the least.
See my previous post right above yours. Just compare Tegra250's BGA package size to the sizes of the surrounding connectors - e.g. the usb-a female connectors, or the d-sub at the far end of the board. The chip's side is almost 2x the width of a usb-a recepticle (~13mm) - i.e. tegra250 is approx 24mm x 24mm package. Compare that to, say, the OMAP3530 (12mm x 12mm 515-pin BGA), or the OMAP4430 (again, 12mm x 12mm BGA) - tegra250 is 4 times the standard OMAP's package size (and ~800-balls strong) - imagine how that would affect the complexity of a handheld's PCB. There's virtually no chance that this particular chip would end up in a pocket-size handheld/handset. Heck, NV themselves are pushing the chip for tablets/netbooks/nettops. And tegra250 is the only tegra2 specimen we now of.
I have no doubt that it would beat a Wii on many fronts, but I still can't help but laughing at effective fillrates on IMRs and that CSAA stuff. Let's just keep it on the level of something slightly better than 2xMSAA, which is fairly good enough for a handheld but not something to write home about either.
In any case I'm not so sure anymore that Nintendo actually has plans for a true next generation handheld in the foreseeable future let alone anything that has to do with Tegra.
Albeit I might be wrong but Tegra2 strikes me as the exact same unit amount as Tegra1 on a smaller process with just twice as much frequency, but would like to stand corrected.
240MHz@40LP
2 FP24 PS
2 VS
2 TMUs
where for each PS ALU I'd say something in the >Vec4 league or something similar.
What do you mean? T1 (120MHz) was on 65LP and T2 (240MHz) on 40LP afaik.
It would be very strange if an ARM11 with 256KB wasn't smaller than 2x Cortex-A9 with 1MB L2 cache; I don't know if much (or anything) would be saved with the other components.
Which of course begs the question I'm sure you and others have asked, how does a 2x clock increase yield a 2-3x performance increase?
gigadude, where is the 1.2gpixel/s number from?
I'm guessing the ~3x perf comes from an improved memory infrastructure.
I was assuming 240Mhz/8 Z/clock, 2 pix/clock, 50/50 mix. I've got one sitting on the desk here, I'm working on getting something interesting running on it.
Apparently nVidia themselves are only saying 2x now (next generation Tegra section on their site). So I take back my question
Is 8 Z/clock an official figure? It's not especially surprising since it's what SGX 53x is capable of (not sure if that number increased in higher end parts), but I haven't yet seen it. Is 50% Z occlusion a standard number for unsorted geometry? That's what you get with random distribution, right?
I wonder what the depth fill performance is like and if depth pre-passes are attractive.
As I said before when I saw the die area I was thinking myself of something in the 4 PS/2VS/4TMU direction. NV's own claim of 2x times performance on their site later put another perspective on the thing as you've seen yourself.
Might be wrong but I think it's 16z on 540/545/543.
Tegra2 doesn't have NEON, this has been confirmed by nVidia: http://tegradeveloper.nvidia.com/tegra/forum/tegra-250-devkit-hw-documentation#comment-546
What do you mean by "if Tegra 2 doesn't have NEON then it has SIMD on it as well"? When NEON isn't available then you only have v6 SIMD instructions (a very small subset of NEON) or some undocumented IP.
I didn't mean what you thought I did, I was saying that if Tegra 2 doesn't have NEON then Broadway (Wii's CPU) has SIMD as an advantage over it.
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