AMD: Pirate Islands (R* 3** series) Speculation/Rumor Thread

http://www.3dcenter.org/news/die-shot-zu-amds-fiji-chip-aufgetaucht

AMD-Fiji-Die-Shot.jpg
 
It's a shame that I have to squint that much.
Some rushed pixel counting of what I squinted to be the area of one of the PHY blocks seems to put the area around 5-6% of die area.
That puts it a little past the top end of my guess based on the PHY area given for HBM (24-30mm2 vs 33-36? from pic).

https://forum.beyond3d.com/posts/1844903/

edit: Eh, I picked the side that might have been cropped. It might be 6-7%.
 
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Relative to the rest of the I/O (PCIe, display, etc.) the HBM phy padding looks quite large, but after all this is a ~600 mm² die. The Hawaii's low-power 512-bit interface could probably occupy less area.
 
Hawaii's memory interface probably isn't that much "low power". In the 390 series the GDDR5 clocks at 1.5GHz (6GT/s).
 
Relative to the rest of the I/O (PCIe, display, etc.) the HBM phy padding looks quite large, but after all this is a ~600 mm² die. The Hawaii's low-power 512-bit interface could probably occupy less area.
Huh? I might remember wrong, but didn't it occupy pretty much 3 of 4 sides of the die?
 
Huh? I might remember wrong, but didn't it occupy pretty much 3 of 4 sides of the die?
I said "probably", since there's no die-shot of Hawaii released, only of Tonga that uses the same phy interfacing.
The case you're referring is Tahiti, I guess?
 
The Hawaii's low-power 512-bit interface could probably occupy less area.
Is Hawaii's interfaces really specifically "low power", though? As I recall the way it was described was simply re-purposing tahiti's old, lower-speed memory controllers.
 
Is Hawaii's interfaces really specifically "low power", though? As I recall the way it was described was simply re-purposing tahiti's old, lower-speed memory controllers.

AMD stated Hawaii's 512bit memory interface was 20% smaller in die area than Tahiti's 384bit memory interface, but reference memory speeds dropped from 1500Mhz to 1250Mhz.
 
AMD stated Hawaii's 512bit memory interface was 20% smaller in die area than Tahiti's 384bit memory interface, but reference memory speeds dropped from 1500Mhz to 1250Mhz.

Again: the speeds went back to 1500MHz in the R9 390 series.
 
AMD stated Hawaii's 512bit memory interface was 20% smaller in die area than Tahiti's 384bit memory interface, but reference memory speeds dropped from 1500Mhz to 1250Mhz.

If that succession of data points holds, that means Tahiti's ~1/5 of its 365mm2 area devoted to GDDR5 PHY translates to ~73mm2 that translates to ~58mm2.
That seems safely above the guesstimated PHY area of Fiji.
 
AMD stated Hawaii's 512bit memory interface was 20% smaller in die area than Tahiti's 384bit memory interface, but reference memory speeds dropped from 1500Mhz to 1250Mhz.
Right, not Tahiti. Like, Cayman, wasn't it? All these codenames are getting difficult to differentiate. :p
 
Well, looks like the HBM phy is just about the same area as the Tonga's 6-channel GDDR5 interface. :???:

That seems to fit the numbers for the succession of interfaces from Tahiti through Hawaii as well.

Tahiti's ~1/5 of its 365mm2 area devoted to GDDR5 PHY translates to ~73mm2 that translates to ~58mm2. 6/8 of that is ~44mm2 which is close to the possibly ~6-7% of Fiji for HBM.
 
I'm thinking doing so would put it too close to the R390 in performance.
The difference in performance should be pretty large, since Tonga doesn't clock very high and there's still a big difference in some areas like fillrate.

I think it might have to do with the memory capacity options they would have with the 384bit bus (3GB too few, 6GB too much) and PCB complexity.
 
6GB wouldn't be too much IMO now that the 390 series has 8GB. But I'm sure there are other reasons why they never went 384bit with Tonga.
 
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