DavidGraham
Veteran
So you mean instead of an 8 bank design in DDR3 ? we have 16 now ?It doesn't. DRAMs actually read out a lot more than the send. Basically they read out the whole 8n prefetch in a single cycle and then transfer that out. To enable back to back data out at data rates higher than an individual bank can sustain, GDDR5 uses the concept of bank groups and forced interleaving between the bank groups. There are 4 defined bank groups, each containing 4 banks. Read commands are not allowed back to back within a bank group but can be done between the bank groups. There is a parameter that determines the min timing interval for subsequent reads to the same bank group as well as a parameter for min cmd timing between reads to a different bank.
Alright, as an example lets take a GDDR5 operating at 1GHz(4Gbits) , is it really operating at that speed ? to me a 500MHz memory core speed is more likely considering the 8-bit buffer .