Whole lot of stuff that isn't about AMD Navi *cleanup*

This is false and next time it'd be better to present sources so you can verify your own guesses.



These are the numbers for Q4 2019.


https://www.tomshardware.com/news/a...-share-7nm-makes-landfall-as-price-war-begins

And these are the numbers down to 2016.

Between Q4 2016 and Q4 2019, AMD went from 9.9% to 18.3% on desktop clients, from practically zero in to 4.5% in server, and from practically zero to 16.2% in mobile clients.
Total client probably went from around 3% (9% desktop + ~0% mobile) to 17% in three years. This is a far cry from the numbers you claimed, which you probably saw on some news referring to year-on-year.

Clients don't change CPUs very often and servers even less so. Proof of that is the fact that Bulldozer released in 2011 and 3 years later AMD still had 18.3% of desktop marketshare, probably because it took that much time for people to upgrade from their K10 CPUs to Intel offerings.

These are enormous feats, and AMD's adoption rate has been accelerating.

 

And Dr. Lisa Su said (don't remember if it was their last Earnings Call or "FAD" in march) .. they are on track for 10% unit share in servers in Q2 2020.

 

BTW, I think this belongs to the AMD Execution thread.

 

And according to The Linley Group AMD reached almost 10 % already in April:
https://www.spglobal.com/marketinte...ntel-amd-sets-sights-on-data-centers-57996772

I have no idea, why some people like to spread such nonsense. Anyway, even those statistics, which are not counting enterprise data centers and noncloud installations, says that AMD has about 8 %.

 

According to my understanding, that' 8% of the server configs, nothing is said about the physical number of processors there.

 

Intel offers 4S config, but it's pretty rare, so the number shouldn't be much lower.

 

I almost never see 4S ( i have designed many datacentres "converged infrastructure") its either 2S or monster Power boxes like the E980. The only place your likely to see a 4S intel system is DB and a lot of that comes down to how big your Databases memory requirements are , things like HANA have strict requirements around memory to optane ratios and on the high end you very quickly end up needing a power box because of this. I dont think i have ever seen an intel 8S system.

 

I rather meant, about how many instances are behind each config.

Example:
8 configs a8 from company a, 92 configs b92 from company b.
But there are enough physcial servers in the data center to serve 50 customers config a8, but only 5 for config a92.

I am not saying either figure of report is invalid, just that it's a different metric (IMO).

 

I don't know, because I am not an Nvidia engineer working on Ampere. What I do know, for example, is that the original Titan was limited to far lower clocks when enabling the FP64 mode. If you wanted to have access to FP64 operations at all, clocks would be lower even for FP32. Why? Again, no idea, but that's what it was.

I also know that Pascal P100 runs much lower clocks than GP102 despite the fact arch was identical except for the addition of half rate FP64 in P100.

lol No, it doesn't say so, no. That's just jumping to conclusions, wildly, with absolutely no proof, whatsoever.

 

For that, one needs to follow the HPC and data chips world closely, the 400w figure doesn't really mean the true power consumption of the chip.

NVIDIA introduced a new form factor called SMX with the introduction of Pascal, it was tied to NVLink. The form factor then slowly increased power consumption to allow for either increased clocks, more memory or the prevention of power throttling.

P100 SXM1 is 250W
P100 SXM2 is 300W with raised clocks
V100 SXM2 is 300W
V100 SXM3 is 350W for the same clocks but memory increased from 16 to 32GB HBM2
V100 SXM3 was later upgraded to 450W for the same clocks as well
A100 SXM4 is 400W with 40GB of HBM2

A100 launched with SXM4 right from the beginning.

A100 is an unusual chip, it dedicates a huge chunk of transistors to tensor cores, which now have an extreme increase in IPC, and support more complicated data formats. The chip also comes with a new form factor SXM4, which raises max TDP further for the prevention of power throttling and for the accounting of more HBM2 memory.

So did the V100 compared to Turing.

 

May 26, 2020