BlackAngus
Newcomer
Yes
I believe ars is correct.
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I believe ars is correct.
=)
Well, Well, Xenon CPU and Cell the same??
- Thread starter russo121
- Start date
Said of Xenon processor:
"It will deliver over a teraflop (one trillion calculations per second) of targeted computing performance," he said. That performance would put it just a bit short of a modern supercomputer.
http://news.com.com/Microsoft+sets+...1.html?part=rss&tag=5606366&subj=news
Those numbers sound impressive but I'll know it when I see it.
"It will deliver over a teraflop (one trillion calculations per second) of targeted computing performance," he said. That performance would put it just a bit short of a modern supercomputer.
http://news.com.com/Microsoft+sets+...1.html?part=rss&tag=5606366&subj=news
Those numbers sound impressive but I'll know it when I see it.
Karma Police
Regular
Allard said today at the GDC that Xenon will have "more than a teraflop of targeted computing performance".
http://www.anandtech.com/news/shownews.aspx?i=23950
Take it for what you will.
http://www.anandtech.com/news/shownews.aspx?i=23950
Take it for what you will.
Karma Police
Regular
AH!!!!!!! I was 10 seconds to slow!!!!! 
Well honestly this isnt that much different from the situation we saw with ps2 vs. xbox. The xbox cpu had vastly lower FP performance compared to the ps2 cpu, but made it up for it with the top-of the line graphics unit. In this case, the ps3 cpu is going to be on the order of 3x faster (current speculation-flops) than the xenon cpu. However the Xenon GPU will have a dedicated vertex transform setup, while the PS3 GPU will most likely rely on the Cell's SPE's to transform vertices. Of course this is based on speculation.
I would not be surprised if the PS3 and Xenon games will be close in graphics quality. Also, remember that the Nvidia PS3 part has already been locked down for several months, and it is scheduled to tape out this summer (i believe?). This should put pixel fillrate of the two parts on a similar level. I think we will be in for a treat in the next 12 months.
I'm curious whether or not the PS3 and Xenon will include a dedicated PPU. While I don't doubt that both of these machines will be able to handle hundreds of bones/particles, if the physics calculations were offloaded from the CPU's it would help greatly. Also I'm worried about the 256mb system memory limit on the machines. I hope Sony will push for 512mb so that Microsoft will be forced to follow suite, although this is doubtful at this point... any ideas?
I would not be surprised if the PS3 and Xenon games will be close in graphics quality. Also, remember that the Nvidia PS3 part has already been locked down for several months, and it is scheduled to tape out this summer (i believe?). This should put pixel fillrate of the two parts on a similar level. I think we will be in for a treat in the next 12 months.
I'm curious whether or not the PS3 and Xenon will include a dedicated PPU. While I don't doubt that both of these machines will be able to handle hundreds of bones/particles, if the physics calculations were offloaded from the CPU's it would help greatly. Also I'm worried about the 256mb system memory limit on the machines. I hope Sony will push for 512mb so that Microsoft will be forced to follow suite, although this is doubtful at this point... any ideas?
Megadrive1988
Veteran
Acert93 said:
we are in agreement then, because I did not take it as the IBM CPU having more than a teraflop of performance, but the combined floating point performance of the CPU and G|VPU. or rather, the system as a whole.
everyone should be reminded of the FLOPs performance that MS-Nvidia originally announced (or mentioned) for the GPU of the original Xbox, pre-downgrade: ~140 GFLOPs in 2000.
http://www.sharkyextreme.com/hardware/private_eye/8/
http://www.it-analysis.com/article.php?articleid=1199
http://neasia.nikkeibp.com/archive_magazine/nea/200007/srep_106418.php
note: sometimes you will see 120 GFLOPs instead of 140 GFLOPs for XGPU aka X-Chip
....the final XGPU in 2001 was rated at 80 GFLOPs.
If it is related to the PPE in the Cell, doesn't that mean the Xenon will suffer from the same branch predict deficiency as the Cell that so many people were worried about a few weeks ago?
Megadrive1988
Veteran
I think that all next-next generation consoles, i.e. Xbox3 ` PS4 ` N6 might possiblely get a PPP, a PPU and a RTU
(primative processing unit, physics processing unit and raytracing unit )
whether these are seperate processors or intergrated into the CPUs and GPUs is another thing. probably intergrated: PPU within the CPUs, and the PPP+RTU within the GPUs.
(primative processing unit, physics processing unit and raytracing unit )
whether these are seperate processors or intergrated into the CPUs and GPUs is another thing. probably intergrated: PPU within the CPUs, and the PPP+RTU within the GPUs.
Well, you have to note that a "Raytracing Unit" doesn't really coincide with Nintendo talk about revolutionizing the Videogame industry via the gameplay and the interface and not from the graphical side of the things.Megadrive1988 said:
Also, having a CPU, a GPU, a PPU, a RTU wouldn't coincide neither with their "easy developement" approach they said they'll take with the Revolution.
Vysez said:
Actually in the so called "Peter Isensee leak" document it states that the XeCPU will have 128.128bit VMX registers per hardware thread... ...since the XECPU has six hardware threads I think s1lverbak is actually correct..... the Xenon has 768 - 128bit vector registers alone moving @ 3Ghz just in the CPU core... actually It has three sets of registers per hardware thread according to the article (integer, FPU and VMX) The total of which is not known... I dont know what that calculates to in terms of power though - you guys are better at extrapolating abstract power constructs like that than I am...
"Each core has two symmetric hardware threads (SMT), for a total of six hardware threads available to games. Not only does the Xenon CPU include the standard set of PowerPC integer and floating-point registers (one set per hardware thread), the Xenon CPU also includes 128 vector (VMX) registers per hardware thread. This astounding number of registers can drastically improve the speed of common mathematical operations."
http://forums.xbox-scene.com/index.php?showtopic=231928
randycat99
Veteran
I'm wondering what the thinking here is. I hope it is realized that Cell and Xenon may share common building blocks, that does not then make them equivalent or exchangeable. What makes them unique are the specific implementations of said building blocks (common and not common). Essentially, both draw heavily on PPC componentry plus new stuff. Otherwise, you could argue the GC processor and every Mac sold since 1996 used a Cell processor, which would be ridiculous.
Wrt to the advent of "humongus" number of registers- you have to realize what their baseline of comparison was. Compared to various x86 designs throughout time, yes, it's got a buttload of registers. x86 designs have historically been register-starved. Similarly, PPC designs (and RISC designs, in general) have historically been register-rich, which has contributed well for various PPC desktops through the ages being able to reap competitive/comparable performance with x86 counterparts, while using considerably less transistors in the PPC core. Registers really allow a CPU to achieve performances more in line with the theoretical (within reason). It is a notable step forward coming from an x86 design, but it is not necessarily going to make this era of PPC's perform better than prior generations of PPC's. They have been benefitting from good register complements all along. The same logic should follow when comparing past Intel SIMD designs (SSE/SSE2) to PPC SIMD incarnations (Altivec/VMX, and possibly PS3 SPE's to come). The preponderance of registers will certainly keep performance high, but PPC SIMD's have always come with a good handful of registers.
Wrt to the advent of "humongus" number of registers- you have to realize what their baseline of comparison was. Compared to various x86 designs throughout time, yes, it's got a buttload of registers. x86 designs have historically been register-starved. Similarly, PPC designs (and RISC designs, in general) have historically been register-rich, which has contributed well for various PPC desktops through the ages being able to reap competitive/comparable performance with x86 counterparts, while using considerably less transistors in the PPC core. Registers really allow a CPU to achieve performances more in line with the theoretical (within reason). It is a notable step forward coming from an x86 design, but it is not necessarily going to make this era of PPC's perform better than prior generations of PPC's. They have been benefitting from good register complements all along. The same logic should follow when comparing past Intel SIMD designs (SSE/SSE2) to PPC SIMD incarnations (Altivec/VMX, and possibly PS3 SPE's to come). The preponderance of registers will certainly keep performance high, but PPC SIMD's have always come with a good handful of registers.
Indeed, some models of the AMD29K RISC processors had upwards of a 192 GPRs... IA-64 specifies 128 logical GPRs...
True, but then they've likewise been penalized by stupid compilers that can't register allocate, software pipeline, or trully exploit register-rich non-accumulator based architectures worth a damn...
Actually even x86 designs have been benefitting as well with large qauntities of physical registers and gobs of allocation logic to push register spillage to rename registers...
Also, according to speculation, X2 is an in-order machine, so it makes almost zero sense to have more physical than addressable registers per context. Unless IBM have suddenly decided to go in a register window/stack type direction, I would assume that each thread can use all N (=128?) registers.
AFAICS this would makes a 32 bit per instruction VMX encoding pretty difficult seeing as a 4 op fma (3 src, 1 dst) requires 28 bits for register indexes alone...
It would be really nice to see some GPU freebies (neg, abs, sat, component swizzling and propagation) and instructions (dot product) on the CPU... any rumors on this front?
Regards,
Serge
AFAICS this would makes a 32 bit per instruction VMX encoding pretty difficult seeing as a 4 op fma (3 src, 1 dst) requires 28 bits for register indexes alone...
It would be really nice to see some GPU freebies (neg, abs, sat, component swizzling and propagation) and instructions (dot product) on the CPU... any rumors on this front?
Regards,
Serge
aaaaa00 said:Last I heard there was some extra "special sauce" on the xenon PPC cores compared with the CELL PPC.
Yep I heard MS wanted some of their own tech from their research division in there that IBM found pretty difficult to implement, but eventually did. You won't find that tech in the PPE in CELL.
aaaaa00 said:
Well the other possible 'sauces' would be an increase in pipes for the VMX units for better sustained throughput and the 'sweetest sauce' would be that the VMX units are 2-way SMT capable themselves.
That would bring each Xenon core to 16 Flops per cycle and a tri-core to 48 Flops per cycle and @ 3GHz ~ 144 GFlops. Do you concur?
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