We sez: "A look inside the European PS3"
- Thread starter StefanS
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Doesn't look to be much cut, just a re-shuffle.
Well, where'd those chips in the smaller rightermost boxes get shuffled to?
Two of those, I'd say are moved from the center, and the last would be a chip added in the Eur version, not 'another chip cut'?
LOL, ok you're right... some sort of weird trick my eyes were playing on me where I kept viewing whicher section missing chips as the Euro version. I believe those two 'new' memory chips on the Euro board were moved up from the bottom of the NTSC version.
Rainbow Man
Veteran
I don't know precisely which chuip you're talking about but one of the flash chips was moved from rear side to front in euro version.
So that could be a re-shuffle as well if it's the chip you mean.
Peace.
That would be it I think. Thanks.
I find it hard to believe it would be an SLI bridge since the RSX chip is heavily modified with a FlexIO connection, it is more likely a custom bridge of any kind fast enough for it's purpose. One solution that can be dismissed would be a FlexIO bridge, since the lines are not designed in the same way as the lines between the Cell and the RSX.
If the re-routed signal lines are excluded from the total number of visible connection lines there are about 85 connection lines visible between the RSX and the GS chip that could be used for inter-communication between the RSX and the GS.That is quite a few lines and should make it a likely target for a future inclusion in the RSX. It could possibly be even more lines as well hidden inside the board.
Here are few comparison shots, feel free to check the number of lines:
PAL PCB
NTSC PCB
PAL PCB
NTSC PCB
Close up view of the lines of the PAL version
Front of PCB:
Back of PCB:
Here are the corresponding pics of the NTSC board:
http://img219.imageshack.us/img219/7501/frontofeegspcbhx0.jpg
http://img451.imageshack.us/img451/4343/backofeegspcblf0.jpg
It would be interesting to know the actual die size of the new "GS" chip or the modified "EE+GS" chip. I believe I saw some post about an analyst company that had actually measured the die of the Cell and the RSX (not the B3D article on RSX), but I cannot find it now, maybe it also included the EE+GS chip?
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Indeed, it was a breakdown of every single chip in the system; it's around here somewhere...
Here's the stuff you're looking for...
Beyond3d Article
Nikkei Article (measured with a micrometer caliper)
Here's what Goto had to say on the modified "GS":
But keep in mind his "version" featured a crazy turbobuffer which is completely nonsense IMO. So it might actually be smaller.
Thanks!
The comments that the "EE+GS" was connected to the southbridge sounds a bit strange judging from the placement of the "EE+GS", I wonder if it's just speculation or if they picked apart the board?
12.5 x 7 = 87.5 mm2 is very close to 86 mm2 (EE+GS@90nm see picture below), so I think we can exclude the possibility of any new fancy logic taking advantage of the EDRAM. If the EDRAM could somehow be useful for the RSX to store some stuff in depends on the bandwidth between the RSX and "GS"/"EE+GS". The 85 visible lines are sufficient to have a 64 bit data bus and a separate 16 bit address bus and a few signal lines. I don't know what speed could be reasonable to expect of such a design.
However, if the "EE+GS" was not connected at all to the RSX as goto's article kind of suggests all speculations of the RSX taking advantage of the EEDRAM somehow are moot.
