RSX = Stream Processor!?!

[hugo]

Nerve,

This is what I could find.A thread on Playstation.com's board.
http://boardsus.playstation.com/pla...ssage.id=249598&view=by_date_ascending&page=1

 

[psp111]

Can any devs comment on how, according to PSM, "The final ps3 dev kit is alot faster than they thought (according to the developer)" and according to Engadget blog, "the final hardware kits released to developers in January were even more powerful than originally anticipated"?

If you measure it in Decibels, then yes, they're *much* more powerful than expected.

 

[ROG27]

If you measure it in Decibels, then yes, they're *much* more powerful than expected.

Are you a dev, sir?

 

["Nerve-Damage"]

Nerve,

This is what I could find.A thread on Playstation.com's board.
http://boardsus.playstation.com/pla...ssage.id=249598&view=by_date_ascending&page=1

Thanks, for the link!!

 

[Titanio]

Can any devs comment on how, according to PSM, "The final ps3 dev kit is alot faster than they thought (according to the developer)" and according to Engadget blog, "the final hardware kits released to developers in January were even more powerful than originally anticipated"?

Someone added the "a lot" I think. The original article refers to it just being faster than they expected. Which doesn't really tell us much of anything, and doesn't necessarily refer to an explicit spec upgrade, or one that could be expressed in terms of clockspeed or pipes

 

[Shifty Geezer]

They're referring to the boot up time. It was expected that the Dev kit would take around 2 minutes to boot up from cold start to useable, but it's actually only 1m 23 seconds - Much faster.

 

[j^aws]

Jaws...no
Barbarian smoked something very good..

*shakes fist at Barbarian*

So how much did he smoke?!

 

[j^aws]

I remembered some time ago when someone brought up the probability of using 1T-SRAM which could save transistor count of upto 1/6 the actual amount of a SRAM.Sony has licensed the right to use 1T-SRAM right?

http://www.beyond3d.com/forum/showpost.php?p=658244&postcount=6

Apparently 1T-SRAM is just a marketing name because it's still eDRAM...

 

[Edge]

Apparently 1T-SRAM is just a marketing name because it's still eDRAM

It's not just a marketing name:

1T-SRAM technology also offers the familiar, refresh-free interface and high performance for random address access cycles associated with traditional SRAMs.

Since it's refresh free, calling it eDRAM would be confusing and potentially misleading, even though eDRAM stands for embedded dynamic randon access memory. eDRAM has traditionally been a term used for embedded memory that requires refresh. It's much more accurate to say eSRAM, but that's an unfamiliar term for people to relate to. How about 1T-SRAM?

 

[j^aws]

No, it's not just a marketing name:



Since it's refresh free, calling it eDRAM would be confusing and potentially misleading, even though eDRAM stands for embedded dynamic randon access memory. eDRAM has traditionally been a term used for embedded memory that requires refresh. It's much more accurate to say eSRAM, but that's an unfamiliar term for people to relate to. How about 1T-SRAM?

Well, apparently 1T-SRAM apparently isn't static,

http://www.beyond3d.com/forum/showpost.php?p=658362&postcount=10

...so the actual name is misleading and suggests it's actually SRAM.

I agree, they should've called it "Super eDRAM" or something!

 

[pc999]

BTW do someone knows how does 1T-SRAM compares to L2, I am trying to find that info at sometime by now, but without luck?

Thanks in advance.

 

[stuart_r]

G70

http://www.tomshardware.com/2005/06/22/24_pipelines_of_power/page3.html

is the speed of the G70 does that equal the spec's of the rsx not sure :-S

http://ps3.ign.com/articles/636/636848p3.html

 

[hugo]

BTW do someone knows how does 1T-SRAM compares to L2, I am trying to find that info at sometime by now, but without luck?

Thanks in advance.

Assume L2 is 6T/4T SRAM, here is a site which explains more about 1T-SRAM.It claims that 1T-SRAM just utilizes 1/4 of traditional 6T SRAM.

An old slide documentation from Mosys.:
http://www.icbank.com/catalogue_data/MoSys/pdf/prsn1t.pdf

http://media.corporate-ir.net/media...sentations/MoSyInvestorPresentation011206.pdf

 

[pc999]

Assume L2 is 6T/4T SRAM, here is a site which explains more about 1T-SRAM.It claims that 1T-SRAM just utilizes 1/4 of traditional 6T SRAM.

An old slide documentation from Mosys.:
http://www.icbank.com/catalogue_data/MoSys/pdf/prsn1t.pdf

http://media.corporate-ir.net/media...sentations/MoSyInvestorPresentation011206.pdf

Nice that gives s bit more of info, BTW theres any word on the latencys compared between the two (I have heared that it is worst but how much?).

OT: interesting the Rev is already listed here (2º pdf).

 

[ShootMyMonkey]

Since it's refresh free, calling it eDRAM would be confusing and potentially misleading, even though eDRAM stands for embedded dynamic randon access memory.

Chances are that when they say it "offers a refresh-free interface" it actually means that refreshes are transparent and all associated overhead is hidden. XDR does the same thing, but they still call it DRAM.

BTW do someone knows how does 1T-SRAM compares to L2

Well, if Gamecube's specs are any indication, sustainable latencies for main memory was around 10 ns, and around 6 ns for the framebuffer/texture cache, though that's surely at the RAM itself.

Mosys' own claims say that the latencies are about even with 6T SRAM. However, I'm fairly sure that means 6T-SRAM at the same clock speed. Since there's no way DRAM can really clock up to say, 3 GHz the way the SRAM in L2 cache can, there's no way it's as good. Now if you had a CPU that was clocked to that same speed range, chances are the 1T-SRAM might be a little faster (assuming that we should actually believe Mosys' claims) because a cache also will carry extra logic for set searches and replacement/eviction policies and issuing writebacks and so on.

 

[hugo]

Not sure how it fares between the 2(traditional SRAM and 1T-SRAM).But we're refering to an alternative technology that could probably stand in for the daughter edram chip that the Xenos have.The 1T-SRAM is on chip (shown on page 7 of the 2nd pdf document posted).Noticed the considerable amount of space that could be saved?I don't think the bandwidth between Xenos and its daughter edram chip could be comparable to 1T-SRAM.

 

[Brimstone]

Mosys 1t SRAM isn't just straight DRAM with a fancy name, it's tweaked DRAM.

The obvious solution is to break up the DRAM array into a bunch of little independent arrays with separate row and column decoders. Then you could send a stream of independent row and column addresses to the chip and get back a stream of bytes from uncorrelated locations in the array, with of course some restrictions. In effect, that is the approach that MoSys Inc. takes in simulating SRAM with its DRAM architecture.

Link

 

[inefficient]

Not sure how it fares between the 2(traditional SRAM and 1T-SRAM).But we're refering to an alternative technology that could probably stand in for the daughter edram chip that the Xenos have.The 1T-SRAM is on chip (shown on page 7 of the 2nd pdf document posted).Noticed the considerable amount of space that could be saved?I don't think the bandwidth between Xenos and its daughter edram chip could be comparable to 1T-SRAM.

They are not using SRAM on the Xenos daughter die. They are using eDRAM.

There is basically only 2 kinds of memory - SRAM and DRAM. SRAM uses only transistors to store it's bit. DRAM will use as few as just 1 transistors but will also add a capacitor. In this sense 1T-"SRAM" is a dram because it includes 1 transistor + capacitor.

In a SRAM cell, you basically trap a bit inside some logic and it just stays either 1 or 0 as long as the power is on. 6T-SRAM uses 6 transistors which is quite a bit of chip realestate to store 1 bit.

In a DRAM cell, there is a capacitor (think of as a small battery) that will save the state of the cell but only for a few cycles. After a few moment the capacitor will loose its charege and the cell will die. The only way to prevent it from dying is to read value in the cell before this happens and set it again. This is a refresh. And this is why on DRAM chips there is a complicated mechanism to keep doing this refresh on the chip.

In general: SRAM very fast, uses a lot of transistors, no overhead for refreshing the data.
DRAM ~10x slower than SRAM, uses far less transistors, a lot of overhead to just keep the data integrity.

In Mosys's 1T-SRAM, compared to typical DRAM, your going to get better latencies because they have optimized some of the problems related to saving the state of each bit. But each cell is bigger than a normal DRAM cell. If they used this on Xenos, their framebuffer would have been even smaller.

 

[MfA]

In Mosys's 1T-SRAM, compared to typical DRAM, your going to get better latencies because they have optimized some of the problems related to saving the state of each bit. But each cell is bigger than a normal DRAM cell. If they used this on Xenos, their framebuffer would have been even smaller.

Hmm?

 

[Bigus Dickus]

Each cell has a bigger physical size. If you keep the same die size, that means less effective storage space, hence a smaller framebuffer byte size.