VR-Zone: G96, G94 and G92 @ 55nm

Hmm i think the better way for NVIDIA would be 384-bit memory bus in it`s GPUS. Cheaper to produce (die size and PCB) even using GDDR5.
 
Well, it`s still pretty huge die.
22x22 vs 22x21.5 for G80. It's big sure but it's not huge.

When will we see a GT206 die? ;)
I dunno =)

So, GT200b is still 512-bit?
That's obvious, no? GT200b is supposedly exactly the same as G92b, G94b, G96b -- just a straight die-shrink without any changes to the architecture. GT206 should be the first GPU from NV with GDDR5 support.
 
22x22 vs 22x21.5 for G80. It's big sure but it's not huge.


I dunno =)


That's obvious, no? GT200b is supposedly exactly the same as G92b, G94b, G96b -- just a straight die-shrink without any changes to the architecture. GT206 should be the first GPU from NV with GDDR5 support.

GT206 with GDDR5 support? You have some clues of this or this is only your supposition? ;)

PS. I wonder about NVIDIAs Roadmap leaked from ELSA. There is GT212 scheduled for 1H09 but it seems that it will be still only shrinked GT200 wit the same DX10 architecture. It`s even strange because ATI has claimed that they are going to release Rv870 with DX11 support around the same time.
 
GT206 with GDDR5 support? You have some clues of this or this is only your supposition? ;)
Well i'm thinking that having 256-bit bus and not having GDDR5 support in the 2H08 would be a bit too much even for NVIDIA.

It`s even strange because ATI has claimed that they are going to release Rv870 with DX11 support around the same time.
AFAIR ATI never stated that RV870 will have DX11 support, only that they'll release DX11 GPUs in 2009.
 
So GT206 is going to have "only" 256-bit memory bus? This means that there will be only 16 ROPs and it could be not enough with AA enabled. But i could be wrong of course.
 
So GT206 is going to have "only" 256-bit memory bus?

Probably.

This means that there will be only 16 ROPs and it could be not enough with AA enabled. But i could be wrong of course.

Not necessarily... The ROP partitions could be re-organized to accomodate 8 ROPs per 64-bit memory channel, and that would preserve the current 32 ROP design of GT200. Also there's the possibility of "fat" ROPs capable of processing more pixels/zixels per cycle, negating the reduction in actual ROP count to 16.
 
So GT206 is going to have "only" 256-bit memory bus? This means that there will be only 16 ROPs and it could be not enough with AA enabled. But i could be wrong of course.
GT206 will probably has only 4 64-bit ROPs. The number of ROPs however has nothing to do with their capabilities. Since GDDR5 provides nearly 2x increase in bandwidth per line these ROPs should have 2x more power and one GDDR5 ROP should be able to write 8 C / 32 Z per clock. Plus it may be smart (or not) to go with one clock 8 Z compare for MSAA and faster FP16 writing/blending. Using old ROPs with GDDR5 is pretty pointless.
 
GT206 will probably has only 4 64-bit ROPs. The number of ROPs however has nothing to do with their capabilities. Since GDDR5 provides nearly 2x increase in bandwidth per line these ROPs should have 2x more power and one GDDR5 ROP should be able to write 8 C / 32 Z per clock. Plus it may be smart (or not) to go with one clock 8 Z compare for MSAA and faster FP16 writing/blending. Using old ROPs with GDDR5 is pretty pointless.

The way you're phrased this makes it sound as though the bandwidth increase alone will somehow double the ROP capabilities, but I'm not completely sure that's what you're saying so I'll save my comments until you clarify.
 
The way you're phrased this makes it sound as though the bandwidth increase alone will somehow double the ROP capabilities, but I'm not completely sure that's what you're saying so I'll save my comments until you clarify.
You need to change the ROPs for double output of course. Otherwise you'll just waste GDDR5 bandwidth.
 
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