Transistor Types

[DavidGraham]

With all the advancement made in the field of process technology, some of us -regular folks- are getting quite confused with all the different names and types of field effect transistors that are buzzing around the media. it would certainly help if we knew about what makes them tick.

I understand now that everything seems to be based on Silicon on Insulator manufacturing process, but then different names are thrown in in combination with SOI which complicates matters :


K dielectric:
-Low K
-High K

Gate:
-Gate First
-Gate Last
-Tri Gates (FinFET?)

-Bulk silicon
-Planar silicon

Any help deciphering all of that?

 

[UniversalTruth]

I understand now that everything seems to be based on Silicon on Insulator manufacturing process

??? How did you understand this?

 

[entity279]

For starters, SOI (silicon on insulator) is opposed to bulk silicon. Both define how the manufacturing process handles the layer under which the "semi conducting material" is placed afterwards.

An insulator means, AFAIK, that stuff may be packed closer together and may run faster. And is more expensive.

Bulk means you get none of the benefits nor drawbacks.

SOI is quite dead now. Intel and ( on a different plane of existence ) TSMC have proven they can deliver bulk processes faster and better performing than their competition.

Global Foundries had been the adopter of SOI manufacturing the most chips but it seems to have started to develop bulk processes as well. My feeling is that they will eventually phase out SOI; as the market for fast, monolithic, power hungry CPUs is diminishing as we speak.

 

[3dilettante]

I understand now that everything seems to be based on Silicon on Insulator manufacturing process,

SOI deals with whether there is a layer of silicon dioxide below the surface of the wafer that separates it from the bulk of the crystal.
Bulk, is when the active transistor layer doesn't have an insulator separating it from the rest of the crystal.

K dielectric:
-Low K
-High K

Typically when these are mentioned, they are not discussing the same thing.
Low K dielectrics, when they are mentioned are usuallly in the context of the material surrounding the connecting wires of the metal layers. Lower capacitance between the wires means there is less charge being stored that influences signal propogation, which makes it easier to transmit signals down those wires.

High K is used when discussing the material of the transistor gate oxide, the insulating layer of material between the gate and channel in the transistor. Here, the desire is for stronger electrical influence.
The traditional material silicon dioxide. The problem as gates shrank is that the layer had to shrink with each node in order for the gate to be close enough to sufficiently control the channel, and it was becoming so thin that electrons were tunnelling through the insulating layer. High K replaces the silicon dioxide with a different material that allows for stronger charge interaction between the gate and channel despite being physically thicker.

Gate:
-Gate First
-Gate Last
-Tri Gates (FinFET?)

Gate first and gate last are process decisions as to when the metalized gates are put down.
Gate first follows a more traditional flow, which is less complex but exposes the metal gates to high temperature steps that those materials can be degraded by.
Gate last sets down placeholders for the gates through the high-temp stages and later replaces them with metalized gates afterwards. This is more complex, but it saves the gates from being damaged by earlier process steps and it seems there were some additional beneficial side effects like better strain.

-Bulk silicon

Not SOI.

-Planar silicon

Not FinFET.
FinFET puts the gate on three sides of the channel, so it is no longer just a stack of flat layers.

 

[DavidGraham]

Thanks a lot for the wonderful answers.

??? How did you understand this?

seems I was wrong.

 

[MfA]

SOI is quite dead now.

Progression is quite dead now, whether TSMC figures out how to do finfets for commodity parts any time soon is an open question.

My guess, they will make some excuses and scrap production of finfets at 20nm and we can start to the big wait again for a shrink which finally provides some decent gains other than density (by anyone other than Intel).