CELL architect speaks on future chip design and fabrication

[Brimstone]

Re: CELL architect speaks on future chip design and fabricat

CELL@65 nm won't particularly be better than 90 nm devices on both clockspeed and power consumption, only smaller. So the forthcoming 90 nm devices will give us a good idea of CELL@65 nm's clockspeed and power consumption level.

To state that Cell@65 is no better than Cell@90nm is beyond retarded, infact I can't think of anything to describe how pathetic this has become.

Deadmeats statement seems fine to me. You seem to be taking it out of context.

 

[Panajev2001a]

Re: ...

From current SOI devices at 90 nm, maybe... neither Prescott, nor products based on CMOS4 wil show you anything useful.

1. CMOS4 is not a real 90 nm process.

It depends where you look my man... the GS's logic is pure 90 nm bliss baby

CMOS4 is a 90 nm manufacturing process: wiether it was using 90 nm ASC9 e-DRAM or not.

Still, CMOS5 is a 65 nm process with SOI ( two big differencies ).

 

[Paul]

Deadmeats statement seems fine to me. You seem to be taking it out of context.

When people learn how to understand that Cell and Broadband Engine are two different things(EG: Cell is an architecture and BE is the actual PS3 CPU made from Cell) is the day I will jump for joy.

Because there is no "Cell at 90nm" No "Cell at 65nm". BE is a seperate offshoot off the Cell project in which Sony and Toshiba are working on, and which they will mass produce in Toshiba, Sony and now East Fishkill

 

[Deadmeat]

It depends where you look my man... the GS's logic is pure 90 nm bliss baby

According to SI, they found no 90 nm nodes inside PSX2OAC.

CMOS4 is a 90 nm manufacturing process: wiether it was using 90 nm ASC9 e-DRAM or not.

Where are 90 nm nodes then? More than that, there are the benefits of a true 90 nm process? PSX2OAC should have measured 65 mm2 if it were a true 90 nm device; it doesn't.

Still, CMOS5 is a 65 nm process with SOI ( two big differencies ).

I don't think people trust Sony's claims on process technology anymore.... Unless they can produce the goods, Sony's "65 nm" is really like 90 nm by everybody else's standard...

 

[Panajev2001a]

It depends where you look my man... the GS's logic is pure 90 nm bliss baby

According to SI, they found no 90 nm nodes inside PSX2OAC.

No, according to "the sample of the EE+GS@90 nm that they examined" SI based their analysis.

They said that in the "dense logic area" they examined the cross-section of, there was n o 90 nm logic.

Sony and Toshiba admitted that the EE ortion of the chip was not fully shrunk to 90 nm design rules and that the e-DRAM does not use their 90 nm library ( ASC9 ), but that the GS core was indeed redesigned respecting commonly accepted 90 nm standards.

SI did not make the exact claim "there is no trace of 90 nm logic in the whole chip, nowhere, nohow", they were careful in what they stated and there was a reason.

CMOS4 is a 90 nm manufacturing process: wiether it was using 90 nm ASC9 e-DRAM or not.

Where are 90 nm nodes then? More than that, there are the benefits of a true 90 nm process? PSX2OAC should have measured 65 mm2 if it were a true 90 nm device; it doesn't.

Maybe 86 mm^2 was low enough in terms of die size for them and they enjoyed the 8 Watts of power consumption better.

Maybe it was cheaper for Sony to push for a mixed part like thy did, you always seems to miss the business side of things when it could be advantageous to Sony.

Still, CMOS5 is a 65 nm process with SOI ( two big differencies ).

I don't think people trust Sony's claims on process technology anymore.... Unless they can produce the goods, Sony's "65 nm" is really like 90 nm by everybody else's standard...

Ahem... when will you understand that when you examine CMOS5 you are bringing MORE than SCE's reputation ( or Sony;s one ), you are calling out Toshiba and IBM as well which are all working towards sub-90 nm and sub-50 nm manufacturing processes ( Toshiba is co-developer of the CMOS4, CMOS5, CMOS6 project and IBM licensed its SOI technology to Sony and helped both Sony and Toshiba with their implementation of SOI in sub-90 nm manufacturing processes ).

You know, making such claims about IBM ( and you are in an inirect way ) could have got you promoted to the position of cement pillar in a local highway 20-30 years ago ( no, I am not wishing this upon you )

Also, when did you ever trust any word coming out of Sony's mouth that was remotely positive for the company ?

Please...


Edit: Answer to PMs, all-right ?

 

[Quaz51]

maybe interesting detail on IBM bluegene chip...

http://www.linuxdevices.com/articles/AT7249538153.html

System on Chip (SOC) technology integrates most compute node functions -- processing, message handling, three levels of on-chip cache, floating point units, routing hardware and more -- into a single ASIC built on a 0.13-micron process, with an 11.1 mm square die size. Each ASIC contains two PowerPC processors running at 700MHz

The nodes themselves are physically small, with an expected 11.1-mm square die size, allowing for a very high density of processing. The ASIC uses IBM CMOS CU-11 0.13 micron technology and is designed to operate at a target speed of 700 MHz, although the actual clock rate used in BG/L will not be known until chips are available in quantity

 

[Deadmeat]

...

11.1 mm square die size

11.1 mm x 11.1 mm = 121 mm2 <- Includes 2 PPC440 and 4 MB eDRAM

Suddenly, Blue Gene ASIC doesn't look so tiny anymore....

 

[MfA]

11.1 mm square is a rather strange way of saying it, the chip is indeed 121 mm2. The most up to date public info on Bluegene/L Im aware of is at http://www.llnl.gov/asci/platforms/bluegene/agenda.html

 

[nobie]

Re: ...

11.1 mm square die size

11.1 mm x 11.1 mm = 121 mm2 <- Includes 2 PPC440 and 4 MB eDRAM

Suddenly, Blue Gene ASIC doesn't look so tiny anymore....

Especially when you consider there's 65,536 of them in BlueGene/L, for a total of 131,072 CPU cores! That's not uncommon for a supercomputer, but it boggles the mind

 

[Panajev2001a]

Re: ...

11.1 mm square die size

11.1 mm x 11.1 mm = 121 mm2 <- Includes 2 PPC440 and 4 MB eDRAM

Suddenly, Blue Gene ASIC doesn't look so tiny anymore....

The ASIC uses IBM CMOS CU-11 0.13 micron technology