45 nm is coming

[Panajev2001a]

Sony, Toshiba to develop next-generation chip
Reuters, 02.12.04, 3:34 AM ET




TOKYO, Feb 12 (Reuters) - Sony Corp <6758.T> and Toshiba Corp <6502.T> said on Thursday they plan to each invest 10 billion yen ($95 million) to jointly develop a microchip that will be smaller and more powerful than any now available.

The planned next-generation semiconductor will have 45-nanometre circuitry -- even narrower than the circuitry planned for "cell", a 65-nanometre microprocessor being developed by the two companies and IBM Corp (nyse: IBM - news - people).

"Cell" is expected to power Sony's next-generation game console.

A nanometre is one-billionth of a metre.

"We started working with Sony on developing a 65-nanometre system LSI in May 2001 and that project will finish up in March. We consider this an extension of that joint project," said Toshiba spokesman Junichi Nagaki.

Toshiba and Sony target completion of a 45-nanometre system LSI (large-scale integrated) -- a high-end microchip that combines multiple functions on one piece of silicon to power everything from DVD recorders to game machines -- by late 2005.

Sony has invested more than 300 billion yen since 1999 to develop and shrink the chips to power the PlayStation 2 (PS2) by almost 80 percent. By creating a smaller chip, Sony can produce more per 200-millimetre (eight-inch) wafer and reduce costs.

Initially, Sony used 180-nanometre processing technology to manufacture the PS2 chips, but it has gradually moved to narrower circuitry in recent years. Sony started manufacturing chips with 90-nanometre circuitry last year.

Sony plans to invest 500 billion yen over the next three years in semiconductors, including 200 billion yen for "cell", which will initially use 300 millimetre wafers and 65-nanometre circuitry.

Toshiba's semiconductor business is the crown jewel of the sprawling conglomerate.

The company forecasts an operating profit of 110 billion yen from its chip operations in the business year to March 31 versus an estimated 140 billion yen for its consolidated results.

The partnership with Sony allows Toshiba to diffuse some of the heavy development costs needed to upgrade its chip technology.

Prior to the announcement, Sony shares closed up 0.93 percent at 4,350 yen and Toshiba shares finished up 2.36 percent at 434 yen. The Nikkei 225 average <.N225> rose 0.91 percent. ($1=105.35 yen)

Copyright 2004, Reuters News Service

http://www.forbes.com/home_asia/newswire/2004/02/12/rtr1257832.html


Let me post somethign about the 45 nm manufacturing process they are working on ( and how it can save money for chips like the GS 3/Visualizer which are e-DRAM heavvy, but even the EE 3/Broadband Engine should contain e-DRAM ).

Toshiba Develops the World's First Embedded DRAM Memory Cell Technology on Silicon-on-Insulator Wafer

13 June, 2003

TOKYO -- Toshiba Corporation today announced that Toshiba has developed and verified the operability of the world's first memory cell technology for embedded DRAM system LSIs on silicon-on-insulator (SOI) wafers. Toshiba aims to apply the new technology to mass production of system LSIs for broadband network applications in 2006.

The move to ubiquitous computing -- total connectivity at all times -- relies on high-performance equipment. This in turn requires advanced system LSIs integrating ultra-high performance transistors and embedded high-density memory. One promising measure to dramatically raise transistor processing speed is fabrication of system LSI on a new-generation silicon substrate, silicon-on-insulator (SOI). However, the conventional DRAM cell structure is designed for conventional bulk wafers and it is difficult to produce embedded DRAM on SOI wafer.

Toshiba has experimentally fabricated a 96kbit cell array and verified the practical operability of the advanced cell structure with sufficient characteristics required for embedded DRAM system LSIs on SOI.

Full details of the new technology were presented on June 11 and 12 at the VLSI Symposium in Kyoto, Japan.

What is SOI?

Unlike a conventional bulk wafer, the SOI wafer comprises three layers: one single-crystal layer of silicon; a base silicon substrate; and a thin insulator, 1/1,000 the thickness of a human hair, that electrically insulates the single-crystal layer from the substrate, inhibiting waste electronic leakage to the substrate. The result is lower power consumption and higher processing speeds.

Toshiba succeeded in forming embedded DRAM system LSI on an SOI wafer by developing a new DRAM memory cell technology that makes use of the characteristics of SOI wafer itself, eliminating the necessity of capacitors where current DRAM cell stores data. The new memory cell technology, dubbed floating body cell (FBC), will be used for embedded DRAM system LSI for the 45-nanometer generation on.

Principle of Operation and cell structure

Conventional DRAM cell consists of a capacitor, where electric charge is stored, and a transistor that function as switches. The newly developed FBC does not have a capacitor and memorizes data by storing the electric charge in its transistor. Since the transistor works as both capacitor and electric switch, the cell area is half that of a conventional DRAM cell.

Manufacturing process

Compatibility in the manufacturing processes of DRAM cells and logic ICs is a crucial issue for the development of embedded DRAM cell technology for SOI-based system LSI. Toshiba's new process achieves full compatibility without any degradation in the performance of systems LSI. In order to ensure compatibility, poly-Si plug, a buffer layer of poly-silicon, is formed in contact area in memory cell.

Verified Operability

Toshiba's experimental 96Kbit cell array achieved successful operation in all bits, a 36-nanosecond access time, 30-nanosecond data switching time, and 500-millisecond data retention time (at 85 degrees C). The results demonstrate that the new FBC technology can be applied to system LSI integrating DRAM cells with megabit or greater memory capacity.
Note:

1 nanometer = one billionth of a meter

As you cna see the area needed by the e-DRAM memory cell is greatly reduced and this means saving quite a bit of money for high volume chips that make at least decent use of e-DRAM in their designs.

This should be the basis for CMOS6 ( the 45 nm manufacturing process co-developed by Sony and Toshiba ) and for the next-generation e-DRAM manufacturing process for the two companies.

Toshiba is the current partner of Sony for what concerns e-DRAM development.

Until the 130 nm generation they used e-DRAM co-designed with Fujitsu, but then they moved onto a new e-DRAM design ( more efficient, suing trench capacitor structure instead of the older stacked capacitor streucture which caused higher heat and reduced the maximum switchign speed of the logic transistors ) co-designed with Toshiba.

http://www.toshiba.co.jp/about/press/2003_06/pr1301.htm


The new 45 nm announcement in Toshiba's own words:
http://www.toshiba.co.jp/about/press/2004_02/pr1201.htm

 

[nobie]

Eh, this is just PR from Sony and Toshiba. Since as the article says Cell is targetted at a 65nm process, development of 45nm technology does not impact Cell's development WRT PS3.

 

[Panajev2001a]

Eh, this is just PR from Sony and Toshiba. Since as the article says Cell is targetted at a 65nm process, development of 45nm technology does not impact Cell's development WRT PS3.

Ahem...

Press releases
IBM, Sony, SCE and Toshiba to Jointly Develop Chip-Making Process Technology

Powerful Alliance is Formed for Semiconductor Processes

TOKYO, JAPAN and EAST FISHKILL, N.Y., April 2, 2002 -- In a unique collaboration, IBM, Sony Corporation, Sony Computer Entertainment Inc. and Toshiba Corporation have signed a multi-year agreement to jointly develop advanced semiconductor technologies based on silicon-on-insulator (SOI) and other IBM materials advances. This will lead to the development of high-performance, low-power chips necessary for a wide range of future electronic products - - from digital consumer applications to supercomputers.

The team will spend several hundred million dollars over four years to develop new process technologies for building chips with features as small as 50 nanometers on 300 mm wafers. Smaller features mean more can be packed on a single chip. The parties plan to use this technology to create system-on-chip (SoC) designs, integrating processor, memory and communications functions, which normally are found on separate chips within a device.

The new processes are expected to be the world's most sophisticated, incorporating advanced chip-making materials pioneered by IBM, such as copper wiring, silicon-on-insulator (SOI) transistors and "low-k" insulation. The use of new designs and materials will be guided by the applications requirements of Sony, one of the world's largest consumers of semiconductors. Toshiba will contribute its high-volume manufacturing capability and SoC technology expertise to meet targeted performance and quality levels.

"The PC is no longer the driving force in semiconductor innovation," said John Kelly, senior vice president and group executive for the IBM Technology Group. "Networking and consumer electronics applications are driving the evolution of a new semiconductor industry -- one based on closer collaboration with customers. This alliance is powerful because of the talents and technologies involved; it is unique in the depth to which the customer is involved, not just in the design of chips for their products, but in the very way they are manufactured."

"Having IBM and Toshiba's technologies with Sony's vast experience and knowledge of the consumer market, truly makes this alliance a winning combination," said Ken Kutaragi, president and CEO, Sony Computer Entertainment and director, Sony Corporation. "Incorporation of these cutting-edge process technologies into various audio, visual and IT products as well as to the computer entertainment system, is expected to bring even higher competitive power to the entire Sony Group."

"Technologies like SOI are essential for high-end and low-power SoC," said Takeshi Nakagawa, corporate senior vice president of Toshiba Corporation and president of Toshiba's Semiconductor Company. "We expect collaboration on SOI process technology to advance joint-development of the next generation broadband processor, and to provide a strong underpinning to our development of leading-edge products. We will apply SOI process technology to broadband processor-based LSI for such applications as a high-speed home gateway and future low-power mobile products."

In a separate agreement, IBM will transfer the latest SOI technologies to Sony and Toshiba. The development work will be conducted by a team of scientists and engineers from all parties at the IBM Semiconductor Research and Development Center (SRDC) in East Fishkill, N.Y. Each party then will have the ability to build the advanced chips in its own manufacturing facilities, products and applications, and for its own semiconductor business customers. A significant portion of IBM's soon-to-be-completed, 300 mm wafer manufacturing facility in East Fishkill will be dedicated to these new processes.

The new alliance framework enhances Sony and IBM's existing collaborative structure by adding the strengths of Toshiba's versatile manufacturing expertise, as the second largest in the semiconductor industry. Integration of the strengths of the parties will facilitate achievement of advanced process technologies for a broad range of products and applications.

About IBM
IBM Microelectronics is a key contributor to IBM's role as the world's premier information technology supplier. IBM Microelectronics develops, manufactures and markets state-of-the-art semiconductor and interconnect technologies, products and services. IBM makes chips for a wide range of devices from the world's most powerful computers to the smallest cell phones. Its superior integrated solutions can be found in many of the world's best-known electronic brands. More information about IBM Microelectronics can be found at: www.ibm.com/chips.

About Sony
Sony Corporation is a leading manufacturer of audio, video, game, communications and information technology products for the consumer and professional markets. With its music, pictures, computer entertainment and on-line businesses, Sony is uniquely positioned to be a leading personal broadband entertainment company in the world. Sony recorded consolidated annual sales of nearly $60 billion for the fiscal year ended March 31, 2001. Sony's Home Page URL: www.world.sony.com.

About Sony Computer Entertainment Inc.
Recognized as the global leader and company responsible for the progression of consumer-based computer entertainment, Sony Computer Entertainment Inc. (SCEI) manufacturers, distributes and markets the PlayStation® game console and PlayStation®2 computer entertainment system. SCEI, along with its subsidiary divisions Sony Computer Entertainment America Inc., Sony Computer Entertainment Europe Ltd. and Sony Computer Entertainment Korea Inc., develops, publishes, markets and distributes software, and manages the third party licensing programs for these two platforms in the respective markets worldwide. Headquartered in Tokyo, Japan, Sony Computer Entertainment Inc. is an independent business unit of the Sony Group.

About Toshiba
Toshiba Corporation is a leader in information and communications systems, electronic components, consumer products, and power systems. The company's integration of these wide-ranging capabilities assures its position as a leading company in semiconductors, LCDs and other electronic devices. Toshiba has 188,000 employees worldwide and annual sales of over US$47 billion. Visit Toshiba's website at http://www.toshiba.co.jp/index.htm.

# # #

We will see CELL based chips in 2005 on 65 nm, but this does not mean that they are not pushing to reduce the time between PlayStation 3's launch date in 2006 and the availability of a 45 nm Broadband Engine.

 

[Deadmeat]

...

You have too much faith in SCEI PR, Panajev. Especially after the PSX2OAC@130 nm fiasco....

Show me a working 90 nm device with 150 million+ transistors, on a die size less than 100 mm2. Then I will believe SCEI.

 

[Panajev2001a]

Re: ...

You have too much faith in SCEI PR, Panajev. Especially after the PSX2OAC@130 nm fiasco....

Show me a working 90 nm device with 150 million+ transistors, on a die size less than 100 mm2. Then I will believe SCEI.

That is a Toshiba PR Deadmeat

I would not call this...

In addition the Sony device uses an advanced two stack low-k dielectric structure. The combination of this dielectric process and the smallest transistor seen so far by Chipworks makes this one of the most advanced processes in volume production today.

...a fiasco.

 

[nobie]

We will see CELL based chips in 2005 on 65 nm, but this does not mean that they are not pushing to reduce the time between PlayStation 3's launch date in 2006 and the availability of a 45 nm Broadband Engine.

My point is, Cell @ 45nm will be the same as Cell @ 65nm, only smaller. The chip (atleast the one going into PS3) is designed for the 65nm process.

 

[Fafalada]

My point is, Cell @ 45nm will be the same as Cell @ 65nm, only smaller. The chip (atleast the one going into PS3) is designed for the 65nm process.

I believe what Panajev is implying is that Sony could design the chip to the point where 65nm yields will be really bad, similar to what they did with GS@25micron.
So while it will still work and be produced as a 65nm chip at first, it will be bloody expensive until the shrink, and cause risks of production shortage etc., banking on the assumption that it will significantly outperform what would be considered a "safe" 65nm design.

 

[Paul]

"We started working with Sony on developing a 65-nanometre system LSI in May 2001 and that project will finish up in March. We consider this an extension of that joint project," said Toshiba spokesman Junichi Nagaki.

The 65nm LSI is the Broadband Engine, it will be finished in March which coincides with the fact that Kutaragi said they will demo Cell tech by March. Expect PS3 specs in march, 5 years after they released PS2's.

 

[Panajev2001a]

My point is, Cell @ 45nm will be the same as Cell @ 65nm, only smaller. The chip (atleast the one going into PS3) is designed for the 65nm process.

I believe what Panajev is implying is that Sony could design the chip to the point where 65nm yields will be really bad, similar to what they did with GS@25micron.
So while it will still work and be produced as a 65nm chip at first, it will be bloody expensive until the shrink, and cause risks of production shortage etc., banking on the assumption that it will significantly outperform what would be considered a "safe" 65nm design.

Ding, Ding, Ding.

 

[gurgi]

hehe

 

[Vince]

So while it will still work and be produced as a 65nm chip at first, it will be bloody expensive until the shrink, and cause risks of production shortage etc., banking on the assumption that it will significantly outperform what would be considered a "safe" 65nm design.

Why do I get this odd sense, almost kinesthetic in intensity and feeling, of deja vu when I read this. It's almost as if I was once part of a 20page debate on the topic or soemthing.

 

[Panajev2001a]

hehe

This time is better then ever

 

[Panajev2001a]

So while it will still work and be produced as a 65nm chip at first, it will be bloody expensive until the shrink, and cause risks of production shortage etc., banking on the assumption that it will significantly outperform what would be considered a "safe" 65nm design.

Why do I get this odd sense, almost kinesthetic in intensity and feeling, of deja vu when I read this. It's almost as if I was once part of a 20page debate on the topic or soemthing.

Oh come on.

 

[jvd]

this is nice. Still waiting for them to put out a 90nm chip though. Then a 65 nm chip. Once that happens then i will get giddy about a 45 nm chip

 

[ChryZ]

this is nice. Still waiting for them to put out a 90nm chip though. Then a 65 nm chip. Once that happens then i will get giddy about a 45 nm chip

The second coffin-nail to this thread, surprisingly from a mod ... how unfortunate.

 

[-tkf-]

Re: ...

You have too much faith in SCEI PR, Panajev. Especially after the PSX2OAC@130 nm fiasco....

Show me a working 90 nm device with 150 million+ transistors, on a die size less than 100 mm2. Then I will believe SCEI.

Wasn't the fiasco that it turned out to be wrong and Sony was right?

 

[jvd]

this is nice. Still waiting for them to put out a 90nm chip though. Then a 65 nm chip. Once that happens then i will get giddy about a 45 nm chip

The second coffin-nail to this thread, surprisingly from a mod ... how unfortunate.

don't see it as a coffin-nail .

Its a simple fact . They are claiming something while not coming good on past claims .

If you want to discuss the future then you have to discuss the present . If they are not using 90 nm tech how do you expect in 4 years they will go from 130nm tech down to 45nm tech ?

Its a valid point and a valid post. If you do not like the fact that its valid that is not my fault

 

[ChryZ]

If you want to discuss the future then you have to discuss the present .

The present was already discussed in another thread, why continue here? This will lead to nothing good ...

 

[jvd]

If you want to discuss the future then you have to discuss the present .

The present was already discussed in another thread, why continue here? This will lead to nothing good ...

It will lead to discussing how valid this claim is . Most can discuss things in a mature tone. There is no reason to fight. I do not want this to be a place where we can't talk about certian things because both sides get upset. Us mods will do our best to keep the flames down so we can all discuss things as freely as possible.

 

[kaching]

I'm sorry, jvd, but you seem altogether too quick to take SI at face value on the PSX issue (with the majority of their "evidence" only available for a fee of $1000...). Only Deadmeat has been quicker than you to proclaim "Sony lied!!!" on this matter, without all the evidence in the case being available.