POWER8 - IBM goes ballistic on big processors

How is the BoB cache supposed to work ? As a per memory channel victim cache ? Or as a massive write coalescing buffer? (or both ?)

Cheers

Depends on what they want to use it for and if they want it to have multiple functionalities. Also depends somewhat on the level/type of RAS features the memory has.

Options include:

Segment/Prefetch caching - Depending on the side of the basic memory block level protection, they may need to load more data from DRAM than they actually need to deliver to the CPU. In that case, the cache or a portion of it can be used to hold the additional line(s) that aren't directly needed by the CPU. For instance if the CPU line size is 64/128B and the DRAM protection is 128/256B. In the case of mismatch cpu cacheline size and dram protection block size it also acts as the RMW buffer.

Hotline/bouncing line/frequent updates - basically there are some patterns of access that will cause lots of updates to memory to occur and/or reads of the same block in memory. In these cases the cache can act as a holding place for these lines, saving power, and reducing effective latency.

General read caching - what it sounds like. basically caching what is read and being able to cache data that through access patterns ends up overflowing the CPU caches.

Stream cache - the controller notices a pattern of a streaming sequence of reads and pre-caches them for reduced latency. Allows for better bank/rank management of the DRAMs esp if there are open DRAM cycles. Results in better latency and increased bandwidth. Same thing for writes, delay write and push them down during dead cycles for a given DRAM.

Victim Cache - cache CPU victim lines that will likely be re-read in the future as a capacity optimization.

It is doubtful that they will run them as simple dumb caches (esp since IBM historically has used 3-4 the number of cache states as others to squeeze out performance) since the capacity ratio is poor wrt to the CPU cache (96 MB in CPU Cache and 128 MB in memory cache). I would assume that they have multiple modes that the memory cache can operate in and that they aren't mutually exclusive. I wouldn't be surprised if it operated in 3-5 separate modes at once to maximize its effective capacity.

For example the segment/prefetch cache functionality would likely only take 1MB, the stream cache another MB, Hotline another MB, victim 8MB or so, etc. So there is certainly enough capacity to have multiple functions using it.
 
I just read this:
http://www.hardware.fr/news/13325/hybrid-memory-cube-production-2014.html
especially this part:
En déportant les contrôleurs mémoires directement dans les puces mémoires, l'Hybrid Memory Cube propose en plus d'un bond net de bande passante la possibilité de repenser les sous systèmes mémoires des processeurs.
Which speaks about the move of the memory controllers into the Hybrid Memory Cube.
I makes me wonder if IBM may have done what it done so bringing HMC to POWER 8 would not imply a redesign of the (main) chip.
Do you think it could be related?
 
How does POWER8 fare against its competitors like the Xeons,arm opterons, and x86 Opterons?

How well will this new processor perform with virtualization,distributed computing, and server clouds?
 
you bumped this thread to ask that?

if you dont know why you would want/need a power processor then you don't want a power processor.

generally they perform very well at there target workloads ( DB, mainframe, etc) but the IBM hardware and software ecosystem can be very expensive.

to directly compare to commodity X86 server on commodity workloads is to miss the point ( a point that is a niche segment thats growing ever more niche) .
 
Power CPUs are big iron mainframe workhorses with focus on reliability and dependability rather than maximum peak performance. They (and the machines they sit in, and as Damnation points out, the software they run) are typically so expensive that if you have to ask the price then you can't afford it. :p
 
IBM has crazy clock speeds too! including a 5.2GHz mainframe CPU.
They're about the most powerful CPUs in the world right along Itanium, Ivy Bridge/Haswell etc., and maybe some Fujitsu Sparc stuff.

Then, AMD stuff is a bit slower and ARM way way slower (but ARMv8, Denver will climb up)

To nitpick, mainframes are mainframes. The POWER7, POWER8 stuff are a class lower, called "mid-range computers".
 
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