Sony is definitely not waiting for PS2 to wind down first
Which reminds me that even the PSOne has not reached official end-of-life yet. With this as reference, PS2 will continue selling for quite some more time. No point trying to wait too long...
Sony is definitely not waiting for PS2 to wind down first
Since CELL is taped out, its logic is locked down - can't afford to sit on your hands while traditional GPU's improve.
A 2007 PS3 could have .45 nm with SOI edram. That should allow for a much higher clock speed than a chip with edram not including the Toshiba SOI technology. The XDR Ram will also get produced on a smaller process allowing for a higher density and faster operational speed. Also the extra time will allow for better development software and tools for game developers.
cthellis42 said:No one is waiting that long--it would be a bit suicidal to give multiple competitors THAT much launch advantage, not to mention game development priorities. Maybe if the PS2 has its current marketshare advantage along with Xbox's technical superiority they would have chosen to wait longer to ride the profits and press for maximum technical advantage, but if they wait it puts not one but two generations from their competitors looking better in comparison. Unless they were assured the the PS3 would cause a blowout of apocalyptic proportions, the longer they wait, the more ground they would be yielding to their competition rather than pressing their advantage.
Meanwhile, they'll likely be creating a PSTwo around the time the PS3 is launched, and will still have companies riding their old systems for quite some time anyway, so it's not like the profits from there would instantly dry up.
Toshiba's embedded-DRAM pact to yield 65-nm technology
By Yoshiko Hara
EE Times
December 15, 2003 (8:09 p.m. ET)
TOKYO — Toshiba Corp. will begin offering by March engineering samples of a 65-nanometer embedded-DRAM technology jointly developed with Sony Corp. The two companies detailed the technology-which involves the smallest DRAM cell size ever reported, 0.11 square micron-at the International Electron Devices Meeting in Washington last week.
Their 32-Mbit memory device is fabricated on a 65-nm process called CMOS5 using six-layer copper wiring with low-k materials. "We are confident that our embedded-DRAM technology takes the lead by about two years among competitors," said Seiji Yamada, chief specialist in the Advanced CMOS Technology Group II at Toshiba's System LSI division.
Toshiba and Sony announced the key technologies-a transistor with a 30-nm gate, the embedded DRAM cell and SRAM cell, and multiple-layer wiring-for the 65-nm process last year. This year the team has come up with a practically operating device.
When DRAM cells shrink, it becomes essential to control the transistors' threshold voltage. To realize a high-performance DRAM cell, the threshold voltage should be maintained high and steady. That is realized by dense ion implantation at the transistor section, but at the same time, the dense ion implants cause leakage of electric charge at the memory capacitor, which deteriorates data retention.
The Toshiba and Sony team resolved this issue by means of a tilted implantation method that inserts a boron ion at a certain angle over the gates. Ions are implanted more densely on both sides of narrow gates; the opposite occurs with wide gates. This stabilizes the resulting threshold voltage, making it "almost flat," said Yoshinori Matsubara, a specialist in Toshiba's Advanced CMOS Technology Group II.
The method also serves to block ions from the memory capacitor section, the companies said. Thus, the team claimed that even the small, 0.11-square-micron cell has adequate threshold voltage and data retention.
Toshiba and Sony have been collaborating on 90-nm and 65-nm process technology development since April 2001. The second development phase, 65-nm process technology, is scheduled for completion in April.
Toshiba plans to begin sampling the 65-nm embedded DRAM in the first quarter, but Sony has not disclosed its fabrication plans. The company is now installing production equipment for 300-mm wafer lines at Nagasaki. Sony will use devices built on the CMOS5 process for its own products first, before selling on the merchant market.
cthellis42 said:Still truckin' along, Toshiba is. Short mention on the Inq:
A REPORT SAID that Toshiba has beaten Intel by making transistors at 45 nanometers which use strained silicon.
According to the Nikkei Business Daily today, Toshiba has included the technique in transistors it is making at 45 nanometers, while Intel is currently restricting the technique to its next generation 90 nanometer process.
The report said that the p and n CMOS transistors use gate electrodes made using the strained silicon technique, and that means they switch over 10 per cent faster than non-strained silicon devices. µ
Sadly Nikkei Business Daily requires credit card registration...
Panajev2001a said:Strained Silicon + SOI + e-DRAM without capacitor == good 45 nm node for Toshiba and Sony.
london-boy said:I agree, something will have to go really really horribly wrong to make Cell any less than "impressive", seen the amount of resources (be it money, IBM-Tosh-Sony alliance, the time it's been in development etc) poured into it...
Hype aside (it's expected, being a Sony product, and especially a Sony product belonging to the Playstation family), the resources put into this architecture are REAL, and i'm not sure how they can possibly f**k this up, cause it would take A LOT to make this "not work".
The only way i can think of is in the case of Sony building PS3 and shipping it to devs without any kind of instructions on how it works. First of all, it's impossible, but for argument's sake, even in that case, there would still be big capable companies willing to spend time harnessing the architecture, hoping to then turn a profit in the long run... And of course that would have nothing to do with the capabilities of the hardware, which would still be "impressive", just a pain to program for.