Toshiba invents world's first e-DRAM technology on SOI

[Panajev2001a]

As you know Toshiba is also developing a 45 nm manufacturing process, called CMOS6 ( CMOS4 = 90 nm, CMOS5 = 65 nm ), with SCE.

http://www.sony.net/SonyInfo/IR/info/presen/eve_03/handout.pdf

Toshiba Develops the World's First Embedded DRAM Memory Cell Technology on Silicon-on-Insulator Wafer

13 June, 2003

TOKYO -- Toshiba Corporation today announced that Toshiba has developed and verified the operability of the world's first memory cell technology for embedded DRAM system LSIs on silicon-on-insulator (SOI) wafers. Toshiba aims to apply the new technology to mass production of system LSIs for broadband network applications in 2006.

The move to ubiquitous computing -- total connectivity at all times -- relies on high-performance equipment. This in turn requires advanced system LSIs integrating ultra-high performance transistors and embedded high-density memory. One promising measure to dramatically raise transistor processing speed is fabrication of system LSI on a new-generation silicon substrate, silicon-on-insulator (SOI). However, the conventional DRAM cell structure is designed for conventional bulk wafers and it is difficult to produce embedded DRAM on SOI wafer.

Toshiba has experimentally fabricated a 96kbit cell array and verified the practical operability of the advanced cell structure with sufficient characteristics required for embedded DRAM system LSIs on SOI.

Full details of the new technology were presented on June 11 and 12 at the VLSI Symposium in Kyoto, Japan.

What is SOI?

Unlike a conventional bulk wafer, the SOI wafer comprises three layers: one single-crystal layer of silicon; a base silicon substrate; and a thin insulator, 1/1,000 the thickness of a human hair, that electrically insulates the single-crystal layer from the substrate, inhibiting waste electronic leakage to the substrate. The result is lower power consumption and higher processing speeds.

Toshiba succeeded in forming embedded DRAM system LSI on an SOI wafer by developing a new DRAM memory cell technology that makes use of the characteristics of SOI wafer itself, eliminating the necessity of capacitors where current DRAM cell stores data. The new memory cell technology, dubbed floating body cell (FBC), will be used for embedded DRAM system LSI for the 45-nanometer generation on.

Principle of Operation and cell structure

Conventional DRAM cell consists of a capacitor, where electric charge is stored, and a transistor that function as switches. The newly developed FBC does not have a capacitor and memorizes data by storing the electric charge in its transistor. Since the transistor works as both capacitor and electric switch, the cell area is half that of a conventional DRAM cell.

Manufacturing process

Compatibility in the manufacturing processes of DRAM cells and logic ICs is a crucial issue for the development of embedded DRAM cell technology for SOI-based system LSI. Toshiba's new process achieves full compatibility without any degradation in the performance of systems LSI. In order to ensure compatibility, poly-Si plug, a buffer layer of poly-silicon, is formed in contact area in memory cell.

Verified Operability

Toshiba's experimental 96Kbit cell array achieved successful operation in all bits, a 36-nanosecond access time, 30-nanosecond data switching time, and 500-millisecond data retention time (at 85 degrees C). The results demonstrate that the new FBC technology can be applied to system LSI integrating DRAM cells with megabit or greater memory capacity.
Note:

1 nanometer = one billionth of a meter

This technology will be important for the 45 nm node, CMOS6, and given the very strong interest in e-DRAM for both SCE and Toshiba ( for PlayStation 3 ) I would expect this to be likely candidate for the CMOS6 process and that would spell a 45 nm SOI CELL processor IMHO.

What do you think ?

 

[Grall]

I think speculation is pointless.

I only care about when a Cell-based console can be bought in stores, and to a certain extent, how much it costs... What process its chips are manufactured in isn't anything that affects me as a consumer. It's pretty pointless and boring stuff really.


*G*

 

[Bohdy]

Hear hear Grall!

First truly intelligent thing said in one of these topics... :?

 

[Panajev2001a]

E-DRAM cells can use SOI to reduce their size ( no need of the capacitor in some designs ) and can offer either lower power consumption or higher frequencies.

In the PlayStation 3 case I am interested by the lower power consumption part and the fact that this technology should roll out by 2006, CMOS6 is not too incredibly far and this is good news.

In the long term this will mean cheaper to manufacture Playstation 3 which might mean that SCE will take non trivial losses on the initial Hardware knowing that it will be a relatively short term situation.

This is turn should mean a better and cheaper PlayStation 3 for the consumers.

 

[nonamer]

No, SOI reduces the heat output of a process, it has nothing to do with size (no capacitor? what kind of volatile RAM is that?!) or speed. It may mean a less hot PS3 in the long run, but won't have any effect initially, unless the PS3 is released on 45nm.

 

[Vince]

No, SOI reduces the heat output of a process... it has nothing to [with]... speed. It may mean a less hot PS3 in the long run

http://www-3.ibm.com/chips/bluelogic/showcase/soi/[/url]]SOI technology improves performance over bulk CMOS technology by 25 to 35%, equivalent to two years of bulk CMOS advances. SOI technology also brings power use advantages of 1.7 to 3 times.

It has nothing to do with size (no capacitor? what kind of volatile RAM is that?!)

http://www.eetimes.com/issue/mn/OEG20030623S0025[/url]]Tokyo - Toshiba Corp. has developed a new cell structure for embedded DRAM on silicon-on-insulator wafers that takes advantage of SOI's specific characteristics. The cell will be an essential technology for the company's system-on-chip designs and will make it possible to integrate larger DRAM cells with the Cell processor, a joint development project of IBM, Sony and Toshiba targeting teraflops performance....

The new DRAM cell does not have a capacitor like a conventional DRAM. Instead, it uses the floating-body effect of the SOI wafer, which causes excessive holes to accumulate in the body under the gate and also causes leakage of electric current. The body then functions as a capacitor.

 

[Panajev2001a]

No, SOI reduces the heat output of a process, it has nothing to do with size (no capacitor? what kind of volatile RAM is that?!) or speed. It may mean a less hot PS3 in the long run, but won't have any effect initially, unless the PS3 is released on 45nm.

It is important if the 45 nm process allows to lower power consumption and reduces the chip size as both things allow to reduce the manufacturing costs of the console.

Vince already replied to your other observations quite well

 

[nonamer]

It looks like this is totally different from SOI on logic. Excusing me of missing the point.

This things is totally new. It's either going to replace standard DRAM altogether or vanish altogether. The benefits are simply too great it seems to be in only one company, unless this is undoable. We'll see.

 

[Panajev2001a]

It looks like this is totally different from SOI on logic. Excusing me of missing the point.

This things is totally new. It's either going to replace standard DRAM altogether or vanish altogether. The benefits are simply too great it seems to be in only one company, unless this is undoable. We'll see.

No need of excusing yourself, misunderstandings are part of life

At the VLSI Symposium, Toshiba described a 96-kbit cell array fabricated on 0.175-micron process rules. Engineers verified the practical operation of the experimental array with a small number of bit failures. Its access time was 36 nanoseconds, data switching time was 30 ns and data retention time was 500 milliseconds at 85 degrees C. The cell is said to be process compatible with logic circuits.

Hamamoto said the cell's specifications satisfy the requirements for commodity DRAMs. The access time may be slow for embedded DRAM, but can be improved in time, he said.

If you follow the link Vince posted this e-DRAM technology should be part of the CMOS6 manufacturing process ( 45 nm SOI ) that they want to use for CELL

Tokyo - Toshiba Corp. has developed a new cell structure for embedded DRAM on silicon-on-insulator wafers that takes advantage of SOI's specific characteristics. The cell will be an essential technology for the company's system-on-chip designs and will make it possible to integrate larger DRAM cells with the Cell processor, a joint development project of IBM, Sony and Toshiba targeting teraflops performance.

 

[Vince]

If you follow the link Vince posted this e-DRAM technology should be part of the CMOS6 manufacturing process ( 45 nm SOI ) that they want to use for CELL

This is where it gets.. complicated. It might fall under the STI process technology which is 10-12S.

Ohh, and this is for the 65nm (11S) generation. Had this linked and forgot to post it:

http://www.toshiba.co.jp/about/press/2002_06/pr1201.htm[/url]]Tokyo--Toshiba Corporation today announced a breakthrough in embedding DRAM on silicon-on-insulator (SOI) wafers that ends the DRAM performance degradation typical of such integration. The new technology will be applied to high-performance system-on-chip (SoC) applications.

Performance enhancements of logic LSI for future broadband applications require integration of DRAM cells and a high performance processor on a single chip. Such a move will support high speed, wide bandwidth data transfers and improve overall system performance...

Toshiba will introduce the hybrid wafer with 65nm process technology, currently targeted for 2005.

It's obvious that process technology will be the unsung hero of this architecture and it's implimentations, for reason we've all heard too many times - no matter what anyone says. Cell looks to be a SOI based IC, as opposed to the bulk (CMOSxx) steppings done by Toshiba/SCEI, that I believe fall under an extention of OTSS. Not 100% sure though.

 

[Panajev2001a]

Vince, Oita #2 for the CELL section implements CMOS5 ( 65 nm ) and so should Nagasaki #2.

From the link you posted we can assume, something we already mentioned before, that even CMOS5 was an SOI based process and that is why Toshiba is so confident that they can easily upgrade the lines from CMOS5 to CMOS6

For CMOS4, CMOS5 and CMOS6 I am referring at this pdf ( CMOS4 through CMOS6 have been co-developed with Toshiba with CELL in mind [for the most part] ):

http://www.sony.net/SonyInfo/IR/info/presen/eve_03/handout.pdf

I still think this e-DRAM technology is for the 45 nm node and not for the 65 nm node.

Depending when they launch CELL this is a good-very good info: if they launch Q4 2005 they can hold on with nice losses on the Hardware because counting that you will be going from 65 nm to 45 nm technology and that the new e-DRAM optimized for SOI will take even less space ( assuming they can improove the access time by that date and I think they can ) SCE would have to endure those nice losses for a not very long period.

With this CMOS6 process, seems SOI based ( I wonder about their 90 nm process... is CMOS4 bulk CMOS or SOI ? I think it is bulk CMOS ).

On your comment about lithography, Vince I agree with you and that is why I am glad STI is working hard on new and innovative manufacturing processes ( long live the unsung hero ).

 

[Vince]

It is important if the 45 nm process allows to lower power consumption and reduces the chip size as both things allow to reduce the manufacturing costs of the console

Yes, to speculate for a moment as I haven't heard this, it's possible that we'll see a situation with CellPS3 similar to the Graphic Synthesizer in 2000.

Where the preformance (eg. switching times, access times, et al.) delta between the 65nm and 45nm embedded SOI processes are close enough that they'll launch with a large and economically unviable IC and then do a relatively fast shrink to 45nm SOI (Perhaps the most advanced embedded SOI lithography process bar-none) and stablize yeilds there. Yet another reason to have a vertical semiconductor structure.

Damn, I've heard this all before somewhere. (runs)

 

[Panajev2001a]

It is important if the 45 nm process allows to lower power consumption and reduces the chip size as both things allow to reduce the manufacturing costs of the console

Yes, to speculate for a moment as I haven't heard this, it's possible that we'll see a situation with CellPS3 similar to the Graphic Synthesizer in 2000.

Where the preformance (eg. switching times, access times, et al.) delta between the 65nm and 45nm embedded SOI processes are close enough that they'll launch with a large and economically unviable IC and then do a relatively fast shrink to 45nm SOI (Perhaps the most advanced embedded SOI lithography process bar-none) and stablize yeilds there. Yet another reason to have a vertical semiconductor structure.

Damn, I've heard this all before somewhere. (runs)

The scenario you are depicting makes sense, I was basically pndering the same idea...

That would be a good thing for CELL and for PlayStation 3 ( and for us the consumers too ).

Your guess is that their current CMOS5 process is SOI too, right ? ( it is mine judging how sure Toshiba guys are about relatively quick upgrade from 65 nm lines to 45 nm lines [CMOS6 is the 45 nm SOI based process, even the article you linked refers to CELL and SCE+Toshiba's work] )

 

[Panajev2001a]

Do not run away, speculate

 

[Vince]

Short answer: No.

My belief (very possible to be incorrect) is that there is two concurrent processes in development:

• STI based xxS process utilizing SOI, Low-K dielectrics, Cu.
• OTSS based CMOSx process that's bulk Cu.

Actually, this is a case where Dave's article can actually be applied correctly (eg. Where not all applications need bleeding-edge technology, thus many companies won't do it).

Take the EE+GS for example, it's down to like 80mm^2. Anytime a IC is <100mm^2 it's per die price is very economical. They've reached a point where they're going to have a massive amount of production capacity (as each line at Nagasaki or OTSS that made an EE or GS, now make an EE AND GS - effectivly doubling production in addition to sheer geometric gains).

So, to shrink it to an SOI/Low-K process might not be worth it economically. It's already cheap, size and thermally effecient - so keeping it to a more conservative and cheap process could make sence due to it's current position. It would be like the companies in that article taking their tiny IC targetting a TV or DVD player and utilizing 90nm SOI for it - it's not economically viable for anything but high-preformance ICs. This is where I see the CMOSx processes being used (along with other assorted Sony processors).

I see the STI xxS processes as being Cell-bound. Again, I sound like a broken record, but it'll be lithography that realizes this thing.

 

[Panajev2001a]

Vince,

why would they build Oita #2 and Nagasaki #2 using CMOS5 ( and later on CMOS6 ) if PlayStation 3's CELL is destined for xxS manufacturing process ?

I would really appreciate if you could expand your thoughts on this.

 

[Panajev2001a]

OTSS based CMOSx process that's bulk Cu.

Nagasaki #2 will use the same process as SCE co-developed it with Toshiba: CMOS5.

What if xxS is the name of the IBM manufacturing process ( which Sony/SCE did license, 100 nm SOI tech back in 2000-2001 ) and CMOSx were the equivalent SCE and Toshiba co-developed to implement CELL ?

 

[Vince]

Why would they build Oita #2 and Nagasaki #2 using CMOS5 ( and later on CMOS6 ) if PlayStation 3's CELL is destined for xxS manufacturing process ?

Are you sure it's CMOS5? I've yet to see them state exactly what it is other than 65nm. Of which we know Cell is SOI and STI is developing the 11S process for Cell for 2005.

http://www.reed-electronics.com/electronicnews/index.asp?layout=article&articleid=CA293669

Again, I could be wrong on this one. OTSS (eg. SCEI & Toshiba) is different than STI.

 

[Panajev2001a]

Putting this:

Sony Computer Entertainment and Sony Invest 200 Billion Yen Over Three Years in Semiconductor Fabrication
Installation of fabrication line supporting 65 nanometer process technology

TOKYO, JAPAN, April 21, 2003 - Sony Computer Entertainment Inc. (SCEI) and Sony Corporation (Sony) announced today that they would invest a total of approximately 200 billion yen over three fiscal years from 2003 to 2005 in the installation of a semiconductor fabrication line to build chips with 65 nanometer process on 300 mm wafers.

With this investment, SCEI will manufacture the new microprocessor for the broadband era, code-named "Cell", as well as other system LSIs, to be used for the next generation computer entertainment system. This investment serves an important role not only for SCEI but also for the Sony Group to develop future broadband network businesses.
Of the 200 billion yen, 73 billion yen will be invested in the FY2003. Installment of a new semiconductor fabrication line for building chips with 65 nanometer process on 300mm wafers will be initiated in SCEI's Fab2, a semiconductor fabrication facility located in Isahaya City, Nagasaki Prefecture. Test production will begin using the new fabrication line, gradually moving on to mass production. Execution of the entire investment will be determined by taking optimal timing, place and allocation into consideration.

Since the spring of 2001, SCEI has been engaged, together with IBM Corporation (IBM) and Toshiba Corporation (Toshiba), in the development of the new microprocessor for the broadband era. Also, since the spring of 2002, Sony has participated in the said three company alliance for the development of the advanced semiconductor process technologies. Research and development of digital signal processing technologies for broadband applications are also being conducted.
By means of this investment, SCEI and Sony aim to effectively conduct test production, and to quickly establish a mass production system with 65 nanometer embedded DRAM process.

"Our work with SCEI and Toshiba on the Cell broadband processor has progressed extremely well," said Dr. John Kelly, senior vice president and group executive for the IBM Technology Group. "We believe the Cell design, and the advanced technologies like SOI with which it will be manufactured, will help change the way people work, play and communicate. This announcement by SCEI/Sony is a confirmation of the progress we've made with the Cell design itself, of our advances in semiconductor technology to help it reach its full potential and of Cell's far-reaching implications for a wide variety of applications."

"One of our key semiconductor business strategies is to place Toshiba in the vanguard in providing processor-centric system-on-chip solutions. Cell, which we are developing with SCEI and IBM, is an essential, next-generation broadband processor, a core product whose sales we will actively promote," said Takeshi Nakagawa, Corporate Senior Vice President of Toshiba Corporation. "We expect to apply Cell to a wide range of applications related to broadband networks, including digital consumer electronics and mobile terminals. Today's announcement by Sony group shows that the Cell development project is proceeding as planned and will accelerate the realization of our expectations."

"The introduction of advanced semiconductor technologies is imperative for the next generation processors that support the broadband network era," said Ken Kutaragi, president and CEO of Sony Computer Entertainment and executive deputy president of Sony Corporation. "Digital consumer electronics and network products to enjoy various broadband applications in homes, such as games, movies, music and digital broadcasting, will play a leading role in the future together with the evolution of PC. Sony Group aims to further develop and expand the market with its advanced semiconductor technologies and a rich and wide array of applications. This investment forms a strategic foundation towards this goal."

"SCEI's Fab 2 already applies the most advanced semiconductor technology to produce high performance LSIs, not only for game hardware but also other electronic products," said Kunitake Ando, President and Group COO, Sony Corporation. "The planned investment will further enhance this advanced semiconductor facility to become a technology driver for the next generation of Sony products. Building on this, Sony's Broadband Network Company, newly established as of April this year, will play a key role in developing next generation electronic devices and linkages to game devices."

SCEI and Sony aim to actively develop businesses as leading companies in the broadband network era and to be the driving forces in the next generation semiconductor business.

About Sony Computer Entertainment Inc.
Recognized as the global leader and company responsible for the progression of consumer-based computer entertainment, Sony Computer Entertainment Inc. (SCEI) manufacturers, distributes and markets the PlayStation(R) game console and PlayStation(R)2 computer entertainment system. SCEI, along with its subsidiary divisions Sony Computer Entertainment America Inc., Sony Computer Entertainment Europe Ltd. and Sony Computer Entertainment Korea Inc., develops, publishes, markets and distributes software, and manages the third party licensing programs for these two platforms in the respective markets worldwide. Headquartered in Tokyo, Japan, Sony Computer Entertainment Inc. is an independent business unit of the Sony Group.

About Sony
Sony Corporation is a leading manufacturer of audio, video, game, communications and information technology products for the consumer and professional markets. With its music, pictures, computer entertainment and on-line businesses, Sony is uniquely positioned to be a leading personal broadband entertainment company in the world. Sony recorded consolidated annual sales of nearly $57 billion for the fiscal year ended March 31, 2002. Sony's Home Page
URL:www.sony.net/

Together with this:

http://www.sony.net/SonyInfo/IR/info/presen/eve_03/handout.pdf

It seems that Nagasaki #2 1'st floor, destined for CELL production does indeed use the CMOS5 manufacturing process.

I will wait for your thoughts

Thanks for partecipating in this discussion buddy

 

[Vince]

Again, Panajev - they don't state it explicitly. Remember the picture I posted before:

<img src=http://pc.watch.impress.co.jp/docs/2003/0421/sony1_06.jpg height=120 width=150>

For all we know, OTSS (Toshiba, SCEI, sans IBM) could have been extended to sub-90nm for the EE+GS or other bulk ICs. And I already touched upon why this could be adventagous for non bleeding-edge preformance apps.