IBM to manufacture Cell on 45nm SOI, Sony/Toshiba to move to 45nm bulk process

Two cell processors can be connected via IOIF0 to form one coherent Cell domain using BIF protocol

I was going to mention that as well... IMO that's the reason that in the present situation they would probably just go for two Cell chips vs one larger die. Consider also that when IBM laid out that initial roadmap, I don't think they were expecting the 45nm chip to be as large as it presently is... probably on the order of approaching half its present size.

It'll be interesting to see what happens with the architecture and potential increase in cores moving forward.
 
Yeah, it's a bit troubling to see that dual Cell mock-up @ 32nm being larger than the single one at 90nm. What is it about the analog components that make it difficult to scale down :?: After 32nm, they'd have to go below the 16nm node to theoretically get to the same point where they are now with 45nm single-Cell, and that's a pretty touchy subject. :p

hm... from another PDF/presentation:

Parallel sequence to be distributed over 8 SPE / 1 PPE
Does that ratio hold true regardless? That means a quad-PPE design to control 32 SPEs... :oops:
 
Yeah, it's a bit troubling to see that dual Cell mock-up @ 32nm being larger than the single one at 90nm.

It's not a dual Cell. It has 32 SPEs and 2 PPEs.

And I don't think it's a real mock up. It looks like a cut and paste photoshop job based off the current Cell @ 45nm photo.
 
That's what I meant when I mentioned "your mock-up" in response to Quaz's photo. Obviously, it's not an official mock-up as Quaz mentioned in that post. ;)

What I was actually trying to state was that it's troubling to see that a 32-SPE, 2-PPE chip is bigger than a single Cell chip when there are two other PPE's to account for at 32nm, assuming a die reduction to 70% between 45nm and 32nm.

fixed wording
 
it's a 30% reduction between 45nm and 32nm
and yes it's a fake that i make for estimate the die size
 
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