TSMC unveils new breakthroughs for Wafer on Wafer technology

Discussion in 'Graphics and Semiconductor Industry' started by DavidGraham, May 2, 2018.

  1. DavidGraham

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    https://translate.google.com.eg/tra...se.de/2018-05/tsmc-wafer-stacking/&edit-text=
    https://www.pcgamesn.com/best-graphics-card
     
  2. Bondrewd

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    I've seen wafer stacking somewhere before.

    A-anyway, it's another mobile-only stuff, the heat density kills it for everything else.
     
    #2 Bondrewd, May 2, 2018
    Last edited: May 2, 2018
  3. Grall

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    Yeah, it'd be like a miniature George Forman grill with two stacked dies facing each other.
     
  4. Tkumpathenurpahl

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    Awesome news. I wonder how much of a paradigm change this will result in as we get closer to 3nm without a clear shrink afterwards in sight.
     
  5. Anarchist4000

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    Keep in mind the whole power profile changes when you start doing this. Once die area ceases to be a limiting factor you operate near threshold voltages all the time. The heat generated by a single die will fall significantly in the process. If designing with a 3rd dimension in mind you can also achieve far shorter wire lengths which can make a difference.
     
  6. Alexko

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    This assumes that you can afford to have each of the mm² of silicon you pay for bringing you less performance.
     
  7. eastmen

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    can't you put something low power / heat under the hotter components. LIke put some edram / sram under the logic
     
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