IBM to manufacture Cell on 45nm SOI, Sony/Toshiba to move to 45nm bulk process

I agree with comments that the application for CELL in consumer electronics is not quite realised yet. However, this would apply to any form of high performance computing in CE, really.

For example, cheaper SoC based solutions have been quite adequate even for high definition entertainment. Even though seeing a realtime preview of your punk hairstyles is cool, I can't imagine the demand for that sort of thing to be great at this time. That is not to say that consumer expectations won't evolve - people will probably expect their fridge to do much more than just cold storage, in the distant future. Until such time, perhaps it makes sense that Sony downscales its involvement with CELL manufacturing.

 

Interesting! Maybe these chips will reach the retail units before next holiday.

Have any anyone peeled off the heatplates of the 65 nm Cells yet and measured the die area? Links?

 

Cell being "too games orientated" may be just a euphemism for "The PS3 isn't sell as well as we thought, so we need to close our own foundry down to cut costs because we can't keep it fully utilized".

 

This was another presentation at ISSCC-2008:

The Cell canot really compete with that solution, even though the Cell @65 nm is probably very close to that die size, but fails at power draw and a more expensive process.

What we don´t know is if Cell may have been ha plan A or plan B solution for TV-sets. But right now we see that it does not fit in, the SPUR-engines of Toshiba may be a candidate though.


Another presentation with Sony involved was titled:
"A 170GB/s 16 Mb Embedded DRAM with Data-Bus Charge-Recycling"

Which relates to a 65 nm low-power test chip. Seems like Sony hasn´t given up on embedded DRAM. I wonder if they are planning anymore die shrinks of the EE+GS chip or if this may be related to the PSP chips if related to consoles at all.

 

SpursEngine, not Spur-engines.

Ayway, frankly IMO I don't differentiate between Cell and Spurs or whatever else... basically it's a matter of whether SPEs and the ISA catch on or not. I think it's done pretty well so far in HPC, but obviously in CE applications there is a strong headwind from solutions like this. Since Toshiba fabs SpursEngine on CMOS, expense and power draw are going to be much more competitive. Not saying that we're going to see a huge market push come from that branch of Cell, but did just want to point it out.

 

Yap ! To me, the SPU software library is it.

 

I've tried to understand the different processes, but what exactly is CMOS? I know it's used in video cameras, but isn't that as the imaging chip? The part that actually recieves the light and transforms it to electronic signals. Tried to read on Wiki but didn't get much.

 

Maybe this link can help : http://ieeexplore.ieee.org/search/c...Text=(CMOS<in>jn)++<and>&runsearch=Run+Search

 

Thank you for the link, i didn't get much however... actually that kinda scared me, looked a wee bit so sciency for me.

 

The thing to understand here really is that CMOS is a bulk process that yields relatively cheaper and and lower power chips mm for mm than SOI, though part of the power savings is associated with the lower clock speeds. Yes, CMOS is an imaging sensor reference as well, but as with the more mainstream applications refers simply to the 'type' of imaging sensor; one fabbed via complementary metal oxide semiconductor lines and equipment. Although they're both a branch of the same fundamental tech, CMOS image sensors and the CMOS lines that produce DRAM, flash, and complex ICs are generally separate due to the specialization that goes into the imaging lines.

 

I see, thank you for clearing that up to me, much appreciated. Would developing CELL on CMOS tech bring any positive impact on the PS3 or is it stricly for other mainstream CE devices? I've been kinda miffed that Cell isn't in everything from TVs and music players to lampshades and glowsticks by now, the idea sounded very appealing when it surfaced.

 

It would bring benefit; namely it would make it cheaper to produce, and nominally lower power as well. But the reason why Cell in PS3 was on SOI design to begin with is that those clockspeeds wouldn't have been achievable on bulk CMOS. Which is why at least for the foreseeable future, the Cell iterations in PS3 will likely still be SOI.

 

Switching Cell over to bulk for the PS3 would require a significant amount of circuit redesign as well.
Bulk silicon has certain circuits and gates that do not translate over to SOI, and I would think there would be complications going in the opposite direction as well.

There was a paper a while back about a fully synthesized version of Cell, which might enable the automation of some that process, but not without performance cost and burdening the PS3 with another redesign, on top of the circuit refactoring Cell has to go through for a "simple" shrink to 65nm.

Another sunk cost like that might not ever be amortized over the expected lifespan of the PS3.

 

Cell is a CMOS chip. It uses complimentary transistor types to implement its logic.
SOI and bulk are descriptions of the silicon substrate, so it is possible to have a design not using CMOS on a bulk or SOI wafer.
A chip built on bulk silicon is pure silicon throughout.
SOI chemically alters a layer just below the surface of the wafer so that it becomes an electrical insulator.

When transistors are patterned on the wafer, they lie atop this thin layer of insulator. If using Partially-Depleted SOI (AMD and IBM and their partners use this), there is still a thin layer of silicon present between the transistors and the insulative layer. Fully-depleted SOI would run the insulative layer right up to the transistors, but this is still considered only a possible future option by the big chip manufacturers.

What SOI does is isolate the transistors' active regions from the rest of the silicon crystal.
This is helpful in one aspect because this means the electrical influence of a lot of unused silicon beneath the transistors is reduced.
Transistors no longer have to fight to discharge the capacitance of the deeper unsused layers of silicon, as the insulative layer blocks it off.
It also has a somewhat minor effect in reducing a kind of leakage where current flows down into the silicon.

This extra insulative layer is not easy to create reliably as any chemical changes threaten the structure of the silicon crystal and can threaten its purity, so manufacturing the silicon is more expensive. On top of that, yields can suffer because of the extra processing and because SOI's changes to the material affect its ability to handle mechanical stress.

It is also unhelpful in another aspect because of the electrical isolation also means that built-up charge no longer bleeds away into the bulk of the silicon.
This so-called floating-body effect means that an SOI gate might switch differently depending on what state it had in a time prior to its input changing.
For bulk, it is usually a safe assumption that this prior influence is absorbed by the silicon below.

Extra circuitry is used to correct for this, but some kinds of circuits simply fail to work because of it. This is why it's not a simple task to just decide a complex chip should use SOI or bulk. Once you have the circuits designed, you can't assume they will work well if the process changes.

ZRAM is an example of a technology that actually uses this effect to store state between cycles, by using the remaining amount of silicon in Partially-Depleted SOI to store charge between refresh cycles.

 

I think that confusion on ColorMe's part is my fault; when I was first referencing CMOS as it applied to Cell, I was referring specifically Sony/Toshiba's formal 'CMOS4,' CMOS5,' etc. named process designations, which are on a bulk process. It's easy to see where one would then mistakenly view CMOS as something separate from SOI rather than an umbrella over it, because indeed in the manner I was using it it is (ie Toshiba's CMOS5 vs IBM's SOI).

 

Cell 45nm at ISSCC

 

Thats a good info,and with cell going to 45nm maybe sony/ibm/toshiba can drop costs at least US$20 each unit.

(isuppli -> cell 90nm =~ US$90 each...65nm -> US$70/60?)

 

Agh! There's iSuppli again...

Anyway good power consumption numbers; size savings on full node shifts don't seem to be what they used to though.

 

Indeed. Suggests cost reductions and the like on future processors will be compromised as the gains from node shrinks has less impact.