They might have planned for Polaris to be out significantly earlier.
Polaris could have been a 22nm design pushed down to 14nm when that node hit trouble. Vega could have always been the 14nm
Because it's probably faster to convert 22nm design to 14nm than to create whole new chip based on new architecture
Actually substantially different designs wouldn't be implausible because of the memory that is getting used. Maybe Vega is exclusively HBM and somewhat locked to higher tier parts with costs for the time being. The available bandwidth between GDDR5X and HBM wouldn't be insignificant if a certain amount of memory (8/12/16GB) was required. Denser HBM chips may be required before pushing down to midrange products. May have very well been more cost effective to use than writing off the 20nm design and creating a 14nm for GDDR5 with a projected short shelf life before HBM prices decrease. An 8GB HBM2 480 would probably be a bit too much bandwidth and costs for the time being.
What I'm saying is that one of the designs may not have been feasible, at this time, and there would have been significant architectural changes required. Polaris having the same IP as Fiji/Tonga may not have been a coincidence. Maybe GDDR isn't supported with Vega in exchange for a bunch of interconnects for interfacing with MCMs. The voltages and cache configurations could change radically.They already wrote of the 20nm design though
To transition to 14nm from a already designed chip for another node is a lot of money in the order of 20 million + without going into mass production, and to do that with 2 designs and not use one or double back and replace one quickly, will cost more than 20 million + not to mention the possible risk of loss from having two designs overlapping with stock amounts.
So in theory you aren't hedging your bets, you are increasing your bottom line risk.
"Vega generation" can't really require HBM, since it's coming to Raven Ridge too (Zen APU, not the HPC one), which will no doubt deal with DDR4 shared with the CPU-portion. But then, the GPUs use several different IP blocks and gfx ip is just one of them
They already wrote of the 20nm design though
To transition to 14nm from a already designed chip for another node is a lot of money in the order of 20 million + without going into mass production, and to do that with 2 designs and not use one or double back and replace one quickly, will cost more than 20 million + not to mention the possible risk of loss from having two designs overlapping with stock amounts.
So in theory you aren't hedging your bets, you are increasing your bottom line risk.
Require HBM no, GMI links, maybe. For an APU it would be cheap as your GPU would use system memory in most cases. For a discrete, low end card using the link would likely be an unnecessary expense. Linking multiple chips, dual GPU, etc they might still be necessary. Point being, some sort of fabric in the place of the memory controller likely isn't warranted on a mid-range product. Ideally low/mid tier products would be replaced by correspondingly powerful APUs. Throw in a single stack of HBM that can benefit the CPU portion as well for performance variants.
That might help explain why Polaris achieves the same transistors/mm2 gain from the supposedly more dense GF 14nm process as Pascal gets from the TSMC 16nm process.
