Speculation and Rumors: AMD RDNA4 ...
- Thread starter BRiT
- Start date
Frenetic Pony
Veteran
Just "Moar chiplets!", that texturing unit RT traversal acceleration patent AMD hasn't done anything with yet, and the assumption that it will be on TSMC 3(?)nm.
Oh, and likely 2024 release date.
Moar chiplets as in multiple compute die will likely show up on CDNA before it shows up in RDNA.
not likely
Bondrewd
Veteran
It's not even GCD there.
Wonder if I'll ever get tired of telling them they ain't getting any matrix cores in client GPUs.
Not in public, no.
There are some funny amdgpu commits tho.
Got it. Consoles are the devil. NV is a saint. Amd+Intel are accepted.
Now that attitude is defined and agreed, let's get started with the rumors.
For a little while at least.
Not what i ment, i said both ways. Keep it to rdna4 without the involvment of consoles and there will be less noise, less indirect amd vs intel vs nv attacks.
Here's a speculation: They'll go full chiplet, i.e. with multiple GCD as well. Hopefully, they'll have figured out how to present two GCDs as one single device to the driver. Unlike MI250X, which is two separate OpenCL devices.
If they pull that successfully off, it'll become clear why chiplets are a huge advantage. If they'll stick with another round of MCDs attached, then it might become difficult to sustain the edge, since chiplets is a one-off advantage until the others have followed suit.
I guess that's possible, e.g. by having some sub command processor per compute tile, with one main processor on the top. Not much new data flow besides the commands seems needed across the tiles then?
But initially i had assumed chiplets means the same revolution which happened to CPUs when going multi core, so we would see indeed multiple small GPUs.
Harder to saturate, but not impossible. I would still prefer it if it helps with pricing. I don't think this would be as disruptive as many people think. You still have only one VRam for all GPUs, and driver can help with translation of old games.
Though, it's still a revolution. AMDs market share is too small to establish this, and single device is their only option. Maybe this adds some thing to the respect they deserve for pioneering chiplets.
Bondrewd
Veteran
It sits in the base tile being swanky and all.
Windows doesn't have any kind of NUMA system for GPUs though, that's the big difference.
Does it need one? Windows doesn’t handle GPU job scheduling.
Bondrewd
Veteran
Don't need to when the interconnect is high perf 'nuff.
Jawed
Legend
I don't see chiplets ever being more than a one-off advantage, whichever variants of "chiplet" and "stacking" are involved, and however many stages of evolution they go through for GPUs, specifically.
There's no reason to expect NVidia to be more than one generation late with chiplets - it was one generation later with a monster on-die cache.
Maybe RDNA 4 is where this happens:
DIE STACKING FOR MODULAR PARALLEL PROCESSORS - ADVANCED MICRO DEVICES, INC.
<div p-id="p-0001">A multi-die parallel processor semiconductor package includes a first base IC die including a first plurality of virtual compute dies 3D stacked on top of the first base IC die. A f
www.freepatentsonline.com
So we have:
- active interposer die (AID) - graphics control processor and last level cache
- shader engine die (SED) - corresponds with shader engines seen in current RDNA GPUs
- multimedia and I/O die (MID) - crap that belongs on a cheap process.
Leoneazzurro5
Regular
Maybe solutions with 4 "GCD" (shader dies?) at the top range, then lower ranges could use 3 or 2, while lowest end could be still monolithic.
It would be interesting to know if the memory interconnection will be something like RDNA3 (most probable) or another new solution.
It would be interesting to know if the memory interconnection will be something like RDNA3 (most probable) or another new solution.
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Bondrewd
Veteran
Correct.Might we see some chiplets on mid range / entry level this time?
Blackwell is still monodies so...
Bingo bingo bingo they call it "true chiplet" design (even if it looks like Ponte Trainwreccio).
… however you may call those and whereever you draw the line between one (GDC) and the other („graphics processing stacked die chiplet“).
As I understand it, the big difference is that GCD contains the command processor, while the SED is just arrays of shaders, and command processor is on the base die.
This patent is different from the earlier AMD stacked GPU one in that memory controllers are moved form the SEDs to the base die with the cache, and instead of having different size base dies for different products, they appear to be making one design and then connecting them with stacked bridge chips.
I like the design. It requires a ridiculous level of confidence in the hybrid stacking process, but if there's one company on the planet that can build that confidence, it's probably AMD.
There's of course the obligatory caveat that just because a company patents something doesn't mean that they are building it any time soon, or ever.
