shaders units RISC or CISC?

[mboeller]

Kind of pointless isn't it. A bunch of nimrods talking about stuff they have no clue about. (with me at the top of the list).

Ouch;

and that to SimonF; _the_ PVR chip designer @ IMG (at least the only one I know of there ).

 

[Dio]

Nimrod: In the Bible, a mighty hunter and king of Shinar who was a grandson of Ham and a great-grandson of Noah.

I thought of the AWACS plane with the fat nose and fat arse that never worked properly myself. But there you go.

 

[mr]

Everytime I read CISC and RISC in the same sentence John R. Mashey comes to mind.

 

[Simon F]

Nimrod: In the Bible, a mighty hunter and king of Shinar who was a grandson of Ham and a great-grandson of Noah.

I thought of the AWACS plane with the fat nose and fat arse that never worked properly myself. But there you go.

Well so did I, but I thought it had to be named after something so I went and checked. Apparently it can also mean rebellion. <shrug>

Everytime I read CISC and RISC in the same sentence John R. Mashey comes to mind. [icon_smile.gif]

That's quite a read. Thanks for the link.

 

[Dio]

Very interesting article, thanks. Some resonance on the web this week in the notes (can't find link) that Linus has made about the superiority of x86 vs. IA64. One comment he made echoes Mashey here:

General comment: this may sound weird, but in the long term, it might be easier to deal with a really complicated bunch of instruction formats, than with a complex set of addressing modes, because at least the former is more amenable to pre-decoding into a cache of decoded instructions that can be pipelined reasonably, whereas the pipeline on the latter can get very tricky (examples to follow). This can lead to the funny effect that a relatively "clean", orthogonal archiecture may actually be harder to make run fast than one that is less clean.

x86 fits in with this pretty nicely - limited addressing modes, which can be pre-decoded giving 'code compression'.

I appear to have drifted OT, just for a change.

 

[Dio]

Actually maybe I haven't - because the Mashey article pretty much clarifies that the shader cores are neither RISC nor CISC, they don't fit in with either

So I'm not OT, the whole topic is

 

[rwolf]

I guess that is why they call it a GPU/VPU and not a CPU. It doesn't follow standard conventions. In some respects it is a pixel pusher and in others it is a real CPU.

 

[rwolf]

Kind of pointless isn't it. A bunch of nimrods talking about stuff they have no clue about. (with me at the top of the list).

Ouch;

and that to SimonF; _the_ PVR chip designer @ IMG (at least the only one I know of there ).

Sorry SimonF, this is more a slam of my knowledge on the subject then yours, no offense.

 

[Gubbi]

Just to go back to the SIMD and CISC/RISC. Think of short vectors as just another datatype which instructions can act on, ie:

byte (8 bit)
word (16 bit)
double word (32)
float (32 bit floating point)
double (64 bit floating point)
Vector of [byte/word/Dword/float/Double]

Only with zero orthogonality to confuse matters (because SIMD is an after though, an extension, in all existing architectures).

Cheers
Gubbi

 

[Heathen]

Nimrod

I thought of the AWACS plane with the fat nose and fat arse that never worked properly myself. But there you go.

That it is and the only prototype of the new variant has one of the wings on upside down.

 

[Dio]

Good ol' British engineering.