shaders units RISC or CISC?
- Thread starter K.I.L.E.R
- Start date
Just wanted to have a different opinion even if it isn't right.
Actually I think that SIMD is not RISC or CISC. A SIMD unit is like a processor by itself. It has its own instruction set designed to work on multiple sets of data, there is no flow control or looping.
I wouldn't be surprised if the 9700 has SIMD units which is why you can do a scalar, texture lookup, and a color operation in one cycle.
I bet it is a hybrid architecture that is a little of everything.
Actually I think that SIMD is not RISC or CISC. A SIMD unit is like a processor by itself. It has its own instruction set designed to work on multiple sets of data, there is no flow control or looping.
I wouldn't be surprised if the 9700 has SIMD units which is why you can do a scalar, texture lookup, and a color operation in one cycle.
I bet it is a hybrid architecture that is a little of everything.
What are RISC and CISC, by you definition?
I think RISC/CISC is an ISA thing. That's why we call x86 CISC and MIPS RISC. It is not about implementation.
Now get back to SIMD. You can have stack based SIMD engine, register-memory SIMD engine, and register-register SIMD engine. Also, the ISA of a SIMD engine can be fixed length or variable length. So IMHO MMX and SSE are CISC SIMD since they are variable length and register-memory model, and Altivec is a RISC SIMD.
I think RISC/CISC is an ISA thing. That's why we call x86 CISC and MIPS RISC. It is not about implementation.
Now get back to SIMD. You can have stack based SIMD engine, register-memory SIMD engine, and register-register SIMD engine. Also, the ISA of a SIMD engine can be fixed length or variable length. So IMHO MMX and SSE are CISC SIMD since they are variable length and register-memory model, and Altivec is a RISC SIMD.
pcchen said:
No, SIMD is SIMD and it is being called from RISC or CISC. SIMD is putting a DSP on RISC chip or CISC chip. RISC is simple instructions, CISC is complex instructions, and SIMD is a single instruction that works on multiple data sets. SIMD doesn't loop, branch, or check for overflows.
And I don't think it is stack based.
I think you would find that SSE2 and Altivec are very similar in the way they work.
I think you are talking about implementation, and I think CISC/RISC is not about implementation, but ISAs. Whether SIMD is executed inside a DSP or not is not important. How its instruction coded is important (regarding to RISC/CISC).
Regarding to this, SSE2 and Altivec are very different. SSE2 has variable length instructions and register-memory model, both are "CISCy" features. Altivec has fixed length instructions and register-register model. They are "RISCy" features.
Regarding to this, SSE2 and Altivec are very different. SSE2 has variable length instructions and register-memory model, both are "CISCy" features. Altivec has fixed length instructions and register-register model. They are "RISCy" features.
Different interface similar instructions.
A VPU SIMD might be designed to handle three vertexes on a polygon, or color operations and address lookup.
They don't have to be same.
An orange is still an orange if you put it in a basket of apples. SIMD is not really RISC and not really CISC. If you were to choose one or the other I would say SIMD is most like RISC, because it has simple instructions.
A VPU SIMD might be designed to handle three vertexes on a polygon, or color operations and address lookup.
They don't have to be same.
An orange is still an orange if you put it in a basket of apples. SIMD is not really RISC and not really CISC. If you were to choose one or the other I would say SIMD is most like RISC, because it has simple instructions.
I wasn't going to get involved in this argument on terms, but there is no reason why a SIMD system can't use either a CISC or RISC approach. SIMD just means you have a lot of processing units that are all executing the same instruction, i.e. they all share the same control unit.rwolf said:
rwolf said:
I think this discussion has gone too far off topic. However, I'd like to remind you, CISC = complex instruction set computer, RISC = reduced instruction set computer. They are more about instruction set architecture, not implementation.
Of course, there is not clear cut in RISC/CISC. For example, RISC ISAs such as MIPS and ARM also has some short instruction extensions, therefore their instructions are not all fixed length. Not to mention that we don't know the internal instruction sets of GPUs since they generally are not public information. So it may be a bit pointless discussing about this
Actually nowadays there isn't much difference. You can pretty much sum it up aspcchen said:
RISC: tends to use fixed-size instructions, usually allowing some redundancy in the instruction set; uses a load-store model for accessing memory
CISC: tends to use variable size instructions with minimum redundancy, trading off decoder complexity vs. program size; allows memory operands to instructions.
Decoder logic has become a lot cheaper (as a percentage of chip cost) since RISC was created, so the main advantage of RISC isn't much of an advantage any more.
Note that there is a third option not mentioned. Both RISC and CISC imply decoding; programmable instructions that don't need decoding are usually termed microcode and might be used instead.
If you want my guess about what ATI is using RISC or CISC look at this..
http://www.ati.com/companyinfo/press/1999/4201.html
http://www.ati.com/companyinfo/press/1999/4201.html
I'd say RISC. Sort of.
The instruction length is almost certainly going to be a fixed width internally. Instructions that use two or three registers simply ignore the last parameter. There is no indirect addressing. While we have modifiers, these are consistent accross all instructions. We also have a fairly generous supply of general purpose registers.
The main difference I see is that most RISC machines are designed to be pipelined. Pixel shaders are not.
Complex instructions are virtually always performed by a macro.
The instruction length is almost certainly going to be a fixed width internally. Instructions that use two or three registers simply ignore the last parameter. There is no indirect addressing. While we have modifiers, these are consistent accross all instructions. We also have a fairly generous supply of general purpose registers.
The main difference I see is that most RISC machines are designed to be pipelined. Pixel shaders are not.
Complex instructions are virtually always performed by a macro.
I don't know about pixel shaders, but I'd say that ATI's Vertex shader is pipelined. Avoiding data dependencies on adjacent instructions seems to make it run faster than having each instruction depend on the previous one. That, to me, indicates some overlap of instruction execution.Squigs said:
Simon F said:
This is the case with the GeForce 3 as well. The Vertex Shader Latency seems to be twice the throughput, so yes, in the case of Vertex shaders, we do see pipelining.
Pixel shaders seem to cycle through a batch of fragments and wait for the instruction to be complete on the first one before executing the second instruction. Not sure if that makes them pipelined or not. The second instruction does start while the first instruction is still active.
Mulciber said:
So if you had to create a floating point unit for a GPU and you had licensed the MIPS core would you write the floating point unit from scratch.
I bet they used it as a reference point which is why their 24-bit calculations run as fast as Nvidia's 16-bit.
You'd just use a silicon design tool to generate the circuits for you.rwolf said:
Do they? Doesn't the Nvidia chip run at a much higher clock rate?
Anyway, I think to summarise this whole thread, the shaders are
Code:
Shader_Implementation = (RISC || CISC || SIMD || VLIW || PIPELINED || MICROCODED);Similar threads
