?s about die size and so...

[pc999]

First, in the XB2 patents both CPU and GPU had access to cach memory, if that is true there is any change to get a CPU and GPU with their own silicone,e.g., not unified die size, e.g. to diferent processors?
If it is only one die size (unified) there is any benefict from that, like price, performance etc...?

Second, if we think in a processor made for 90nm, and the company decide to launch later in: the 65nm, the same die size,same features/speed, but more memory.How much more eDRAM/cache could they put to complet the original die size?Would the beneficts (performance) worth the price?

Thanks in advance.

 

[j^aws]

First, in the XB2 patents both CPU and GPU had access to cach memory, if that is true there is any change to get a CPU and GPU with their own silicone,e.g., not unified die size, e.g. to diferent processors?
If it is only one die size (unified) there is any benefict from that, like price, performance etc...?

Putting as many things as you can on die is a benefit to performance but you have to weigh that up against the heat dissipated, the clockability and the lower yields of the larger die size.

Put simply would the CPU+GPU on 2x100 mm2 dies be better than an integrated 1x200 mm2 die? I'd wager the integrated die would cost more due to worse yields but perform better...

Second, if we think in a processor made for 90nm, and the company decide to launch later in: the 65nm, the same die size,same features/speed, but more memory.How much more eDRAM/cache could they put to complet the original die size?Would the beneficts (performance) worth the price?

If you keep the same die size but reduce from 90nm to 65nm, you should have ~2x the transistor budget. If you have say, a die of 200mm2 at 65nm, then from what you describe, your asking how much eDRAM/cache can you place in 100mm2 of that die? I'd say alot!!!

I did some rough calculations/ extrapolations below for the integrated EE+GS,

http://www.beyond3d.com/forum/viewtopic.php?p=353174#353174

64MB of eDRAM ~ 55mm2 at 65nm

Basically if you started with a 110mm2 die at 90nm, then you can add an extra 64MB of eDRAM to the extra available area, i.e. half the die at 55mm2 at 65nm.

Obviously Z-ram or Toshiba capacitorless eDRAM would be more area efficient. Also cache is alot less area efficient than eDRAM.

EDIT: Correction from 114mm2 to 55mm2 for 64MB of eDRAM at 65nm.