I never said that it had to be Cadence/Tensilica it could be AMD who make a chip for offloading some rendering tasks but I think it would make more sense to use a chip that's already being made & will continue to be made & sold to other customers.
Revenge of Cell, the DPU Rises *spawn*
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I never said that it had to be Cadence/Tensilica it could be AMD who make a chip for offloading some rendering tasks but I think it would make more sense to use a chip that's already being made & will continue to be made & sold to other customers.
I actually think that whereas it is going to be called DPU the use of dedicated units will happens more and more and the interfacing between those units is only to get better. ARM sort of illustrated such usage in the presentation of the Mali-T880.
Onq I share your pov we could see (existing) dedicating units take more relevance in gaming technology. I don't expect "new" units and it has to be units widely used, and I mean widely. The best contender I see is the "image processor" whatever they are called, I speak of those dedicated units manufacturers goes through the pain of developing to process those nice but heavy pictures, /VPU looking at the width of the thing qualcomm came with in their last SOC. If they do it it is because those devices are significantly more efficient at the job than GPU. Along with compression/and decompression I could see those devices put to great use to rework textures, post processing.
I wonder how those "things' could fare at texture procedural generation.
Onq I share your pov we could see (existing) dedicating units take more relevance in gaming technology. I don't expect "new" units and it has to be units widely used, and I mean widely. The best contender I see is the "image processor" whatever they are called, I speak of those dedicated units manufacturers goes through the pain of developing to process those nice but heavy pictures, /VPU looking at the width of the thing qualcomm came with in their last SOC. If they do it it is because those devices are significantly more efficient at the job than GPU. Along with compression/and decompression I could see those devices put to great use to rework textures, post processing.
I wonder how those "things' could fare at texture procedural generation.
Yes it will still be a GPU like all the other AMD GPU's that have Tensilica chips in them.
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Could someone point me to an article on what a DPU is?
Also isn't temporal reprojection a perfect fit for the hardware already in a gpu?
edit - reprojection/temporal reprojection if there's a difference.
Also isn't temporal reprojection a perfect fit for the hardware already in a gpu?
edit - reprojection/temporal reprojection if there's a difference.
Ok, so I think I found the answer to this one in some of the marketing materials onQ posted. They mention firmware upgrades to alter the DPU programming. The thing is, though, that once a DPU is configured a certain way and released in a product, the degree to which you can alter the programming is going to be limited by the need to maintain compatibility with existing software. It may not technically be fixed-function hardware, but practically it will be.
@onQ You've been using marketing materials designed to highlight all of the positive points of these devices to support your point of view. You see how this alone might make some question whether you have a balanced viewpoint on the subject, right? The AMD slides had some balance, but you seem to have only considered the "pro" slide and ignored the "con" one.
I'm not just talking about a DPU I was talking about offloading some tasks to specialized processors but the fact that AMD is already using a DPU for speech recognition, video decoding & so on I used it as an example. it's not a FPGA you're not changing the hardware after you get it on the market but you can update the code that you're running on the chip.
the 360 had those functions running on the EDRAM that allowed some functions to be done with minimal overhead
do you see this as new items or just the GPUs current different operations further split so at console level development you can orchestrate the flow of data through it at an even finer granularity?
D
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Except that is referring to cloud.
Here's a better definition from Tensilica themselves: http://www.edn.com/electronics-blogs/other/4307524/Multiprocessing-5-Dataplane-Processor-Units
In short, a DPU is Cell.
Here's a better definition from Tensilica themselves: http://www.edn.com/electronics-blogs/other/4307524/Multiprocessing-5-Dataplane-Processor-Units
In short, a DPU is Cell.
Actually, SPE's lacked some of the DSP features, despite its detractors loving to refer to SPE's as DSPs.
Except that is referring to cloud.
Here's a better definition from Tensilica themselves: http://www.edn.com/electronics-blogs/other/4307524/Multiprocessing-5-Dataplane-Processor-Units
In short, a DPU is Cell.
Actually, SPE's lacked some of the DSP features, despite its detractors loving to refer to SPE's as DSPs.
Remember when I asked the crazy question: can Sony add fixed function pipelines to the PS4 after release? It was because I was reading about something like this after Cerny said some crazy things in his interview.
This is what I was talking about when I asked that question.
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It's not Data Processing Unit it's Dataplane Processing Unit
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From the Tensilica engineer quote, I think it means more 'data domain' rather than 'control domain'. The idea is processors that can deal with data processing as well as hardware while being programmable in a way beyond DSPs. I think. TBH it's basically a marketing term at this point if no-one else is using it. 
Once it all said and done it seems to me that the Cell suffered from an unbalance between cpu and SPU and both suffered from being designed at a time when speed demon designs were fashionable. The Cell also embarked quite a few units (8) as if many cores were a must have feature instead of a necessity. Then the Cell shipped without a proper programming model going as far as exposing the underlying hardware. I would think Cell demise came more from the CPU side than the SPU as the PPE were bad and with the bad start nobody within STI dared to iterate on the design.Except that is referring to cloud.
Here's a better definition from Tensilica themselves: http://www.edn.com/electronics-blogs/other/4307524/Multiprocessing-5-Dataplane-Processor-Units
In short, a DPU is Cell.
Actually, SPE's lacked some of the DSP features, despite its detractors loving to refer to SPE's as DSPs.
As time pass the thing that stands the most out of the Cell design is not that it was heterogeneous /ASM design, the memory model for the SPU, the unbalanced between CPU and SPU resources, the software mode (or lack of)l, the bad CPUs, what really stands stands out in the cold now that time has passed is the width of the SPU, I mean 4 wide?
SPUs were indeed not DPS but they failed at being VPUs, they enforce the SIMD programming model while being as narrow as it gets (~) and multi cores programming as they chose multiple narrow units instead of a single or a couple of bigger ones. Looking at the design again it smells as if LIW or VLIW would have been a better match for SPUs architectures.
Anyway long story short I don't see how the Cell by self can be used as an argument against more heterogeneous design as it lackings might not be related to its heterogeneous nature but others designs choices. There are many successful heterogenous design like mobile SOC and it seems like things are headed toward more heterogeneity.
As we are on that topic those detail about qualcomm Hexagone may interest people around.
http://anandtech.com/show/9552/qual...680-dsp-in-snapdragon-820-accelerated-imaging
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From the Tensilica engineer quote, I think it means more 'data domain' rather than 'control domain'. The idea is processors that can deal with data processing as well as hardware while being programmable in a way beyond DSPs. I think. TBH it's basically a marketing term at this point if no-one else is using it.
But what's the control domain in an soc, cpu, gpu? This one is going over my head.
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