I think they'd be in context automatically. You don't need to worry about the latency, either. All you need is to know how deeply-pipelined the texture units are, and have significantly more register space than that available, so that the pixel pipelines can be fed while the texture pipelines are full or stalled.Jawed said:Presuming you do really mean Xenos, not R520, then I imagine it's much like R520, in fact. The texture pipes can send data directly to the register array.
In order for this to be valid, the batch that wants that texture data needs to be in context, so the scheduler would have to time the batch so that it is ready, too. So there might be a buffer on the texture pipes' output to soak up the unknowable latency of the texture operation.