PSX not at 90nm?

Status
Not open for further replies.

passerby

Regular
Most who observe my posts will note that I am solely a PS2 gamer, so trust that this is not an intended flame bait. Though I have a great fear that I may be starting one. :( Any way, here's the scoop from Semiconductor Insight:

Semiconductor Insights Reveals Sony PlayStation X (PSX) Not Yet Ready for 90nm

FOR IMMEDIATE RELEASE:

OTTAWA, January 29, 2004 — Semiconductor Insights (SI), the leader in technical and patent analyses of integrated circuits and structures, today revealed that Sony's widely publicized 90nm EmotionEngine + Graphics Synthesizer (EE+GS@90nm) found in the PlayStation X (PSX) is still shipping in 130nm technology. "This discovery is contrary to Sony's announcement about this device", said Derek Nuhn, Senior Vice President and Chief Operating Officer of Semiconductor Insights. "Manufacturers, including Sony, are under great market pressure to deliver at 90 nm, but the reality is many are not ready."

The PSX family reinforces Sony's strategy to combine the company's game and electronics technologies. The PSX is currently being promoted as the first Sony system based on the EE+GS@90nm processor, which combines the PlayStation 2's Emotion Engine and Graphics Synthesizer chips onto a single die. Semiconductor Insights removed the EE+GS@90nm chip from the PSX, model DESR-5000, and determined it to be 130nm technology with a die size of 90mm². This is in contrast to Sony's widely advertised claims of 90nm technology and an associated die size of 86² for the PSX.

"We often see discrepancies between announced ship dates and technology nodes, as companies are under increasing pressure to over-hang the market", said Nuhn. "The interesting issue here is how Sony met their announced die size, while implementing the device in the older technology node. As our investigation proceeds, we will be reporting on the PSX in more depth."

For additional details on the Sony PSX chipset, other 90nm devices, and/or related analysis available from Semiconductor Insights, please visit www.semiconductor.com.

About Semiconductor Insights®
Semiconductor Insights helps leading-edge technology companies and licensing professionals attain their product and intellectual property goals by providing in-depth technical and patent analyses of integrated circuits and structures. Our international client base spans Fortune 500 Enterprises, Governments, Legal Firms, Start-ups, and Venture Capitalists. Within the semiconductor industry, we have participated in virtually every major licensing campaign over the past 14 years, and count 47 of the top 50 companies among our clients. For more information, please visit us on the web at www.semiconductor.com

For further information, contact:

Jill Perry
Semiconductor Insights
(613) 599-5145 ext. 4444
jillp@semiconductor.com
 
Not like it would make a whole lot of a difference, but i thought it was 90nm all the way... Does it REALLY matter if it isn't?
Apart from the fact that Sony is lying to the public, which is common practive among corporations these days....
 
V3 said:
which is common practice among corporations these days....

You don't lie about something that can be quantified.


Personally i wouldn't be able to quantify the transistors size in my PSX. I would never buy a PSX anyway.

PR is strong in some companies...

Also, if it is not something important, why informing everyone of a delay in the process if it doesn't affect the production of the product?

I mean PSX exists right, you can buy one in the territories where it has been released, so who cares if EEGS is at 90nm or 13nm...
 
...

Well, that kind of explains why PSX2OAC was larger than expected based on my calculations....

If SCEI has no 90 nm production parts while Intel, IBM, and AMD do, then SCEI is behind, not ahead of, the industry leaders in fab technology curve.

This has great implication for the future of PSX3 and PSP. This fab process transition schedule setbacks might explain why SCEI decided to price the PSP at 48,000 Yen, while reducing the CELL FLOP rating to upto 10x of contemporary PC processors.(~128 GLOPS per chip???).
 
...

Since when is a factual news article a flame???

SCEI lied about the readiness of its process technology and was caught with its pants down, that should be enough to entertain us for a while...

Anyhow, I too am interested in how SCEI managed the die size of 90 mm2 on a 130 nm process. I recall that previous 130 nm EE and GS were ~78 mm2 in die size respectively
 
Re: ...

Deadmeat said:
Since when is a factual news article a flame???

Sony lied about the readiness of its process technology and was caught with its pants down, that should be enough to entertain us for a while...



And you ask why this should be locked..... o_O

U amaze me everytime... :rolleyes:
 
Yes, mod shouldn't really lock this news, its pretty interesting and serious issue too.

Personally i wouldn't be able to quantify the transistors size in my PSX. I would never buy a PSX anyway.

PR is strong in some companies...

Also, if it is not something important, why informing everyone of a delay in the process if it doesn't affect the production of the product?

I mean PSX exists right, you can buy one in the territories where it has been released, so who cares if EEGS is at 90nm or 13nm...

Ohh the ramification is quite serious for Sony. Remember there are alot of public investors putting their money on Sony.

If this is true, Sony has lied to gain investor confidence, and that's not a good thing from any companies.

To consumers it doesn't matter much, but then again this info are mostly PR for investors and that matters.
 
IBL.

I would have to side with Deadmeat on this having implications (not good ones) for PS3.


if Sony lied, and if Sony is behind in process / fab technology, it only shows Sony is not as good as they want everyone to believe.

does it matter that your PSX is 13 nm instead of 90 nm ? no, not for the user, but its not good overall for Sony in the tech race. which is in turn good for Nintendo and MS.
 
Well another reasons for them to use 130nm process, was because they manage to get EE+GS @ 130nm is only 90mm2.

So they probably produce some EE+GS chip on 130nm process as well as on 90nm process.
 
V3 said:
Well another reasons for them to use 130nm process, was because they manage to get EE+GS @ 130nm is only 90mm2.


If what you're saying here is that before getting to 90nm they were producing at 130nm, therefore they have a stock of 13nmEE+GS they are now trying to get rid of by putting them into the first PSX, then it's what i was thinking.
 
...

You just don't move between processes like that easily, since the implementation to each process generation is essentially a redesign and re-verification.

SCEI claimed that PSX2OAC was designed for and was the first 90 nm product out of its fab, that it was ahead of Intel and IBM in fab process ball game. According to this new find, SCEI's 90 nm is not production ready, and this has great implications for PSP, which is an exclusively a 90 nm part.
 
"The interesting issue here is how Sony met their announced die size, while implementing the device in the older technology node. As our investigation proceeds, we will be reporting on the PSX in more depth."

If this is true(them using 130 for first EE+GS) them meeting the die size at 130 is quite an accomplishment..
 
Well, that's just a possible scenario. But you know it takes quite abit of effort to do EE+GS @ 130nm at size of 90mm2.

Its not something you would do again when you can do it @90nm at size of 86mm2.
 
V3 said:
Well, that's just a possible scenario. But you know it takes quite abit of effort to do EE+GS @ 130nm at size of 90mm2.

Its not something you would do again when you can do it @90nm at size of 86mm2.

Good point... I seriously do not know how they could fit both EE and GS ( old revision with stacked capacitors structure for the e-DRAM, the trench capacitor structure was co-developed with Toshiba [ASC9 e-DRAM process] ) with 130 nm technology: the EE was 73 mm^2 in 150 nm technology and the GS in its 6th revision was 73 mm^2 in 130 nm technology.

Think about it for a second: what is likely is that they produced some early EE+GS@90 nm chips with larger than 90 nm masks, thus the final chip using their CMOS4 process ( co-developed by Toshiba and with IBM's IP inside it ) would be 86 mm^2 ( 90 mm^2 in 130 nm and 86 mm^2 in 90 nm technology ? Well, if this is true there go all Deadmeat's claim about Sony not being capable of high transistor density ).
 
...

Whatever the truth is, PSX2OAC numbers look bad next to contemporary Intel Dothan with 150 million transistors crammed into an 88 mm2 die clocking at 2 Ghz.

SCEI has much to learn from industry leaders, and are in no position to teach them a lesson about chip fabrication...
 
Since when is a factual news article a flame???

Since when is this a factual news article? It's a press release, a rather specious way to present findings like this. Considering that SI is essentially claiming to have caught Sony in a lie about a product shipping to consumers why is there no indication that they've tried contacting Sony about this and why must we pay $1000 to see whether their findings are in fact accurate?

Seems more like opportunistic appropriation of permissive press release services for cheap marketing on SI's part, more than anything else.
 
For $1000 you can have the full report

Sony claims to manufacture at 90 nm, but the design rules are relaxed to 130 nm. The e-DRAM trench cells are also laid out using 130 nm design rules. This is a significant advance beyond the 0.25 µm used in the e-DRAM of the Graphics Synthesizer in the PS2 while the logic rules have followed a standard path from 180 nm down to 130 nm.
 
Status
Not open for further replies.
Back
Top