What are we all thinking for the layout of the SoC?
The rumoured CU count is 60 active out of 64. That would lend itself to adding an additional row of DCU's on each wing of the butterfly, and 4 more in the centre (which on the
base model is occupied by cache and primitive units etc).
But then what of the belly of the butterfly with its primitive units, geometry engine, cache, memory controllers etc? Do they all reduce equally well in the shrink to 5nm such that the "non-DCU" part of the GPU doesn't have to be an odd shape and can rectangularly sit in the centre?