PowerVR Serie 5 is a DX9 chip?

[Joe DeFuria]

8 bytes per pixel at 32 bit color output....

NO!! Arrrgghhh....

Quite simply, there is 8 bytes of bandwidth available on a Kyro-II board, for every 1 pixel of raw fill rate.

Kyro-II: 2.8 GB/Sec bandwidth available, 0.35 GPixel/sec fill rate.

In other words, despite whatever "bandwidth savings" is claimed to be saved, Kyro shipped as if it didn't have any, because it shipped with a similar bandwidth to pixel ratio as traditional IMRs. So why should we expect that a new deferred renderer will ship with a lower bandwidth per pixel ratio (which would reduce cost), compared to Kyro?

 

[jb]

AGAIN, my point is there are just as many "flaws" with comparing a Kyro to a TNT, as there are with comparing a "doubled" Kyro II with a GeForce4 MX.

I guess I dont understand the flaws with the Kyro vrs the TNT2. The both had the same specs, same numbe of TMUs, no tnl, ect. Its a lot closer comparison to the K2 vrs MX IMHO. I thought the whole frame was givin the same specs one could be faster than the other?

You cannot ignore the factor of time. If IMRs like the Radeon 9700 were of the same efficiencey as the TNT-2, then I could see your case.

In light of no hard ware we have no other data. Usally looking in the past can give us insight to the futrure, or am I worng?

 

[Joe DeFuria]

I guess I dont understand the flaws with the Kyro vrs the TNT2

It's the same flaw that demalion tries to point out in my comparison. Kyro is a "newer" chip than the TNT2. What it boils down to is that the Kyro is a NEWER chip compared to the TNT2. So it can build in "stuff" for more efficiency because it was designed at a later date.

The Neon-250 is a chip that is actually similar to TNT-2 in terms of timing. I don't recall the specs of Neon (though I think it's a 64 bit bus). Perhaps we can "halve" the TNT-2 in some benchmarks and see how it does against the Neon, to get a more complete perspective.

Again...to make a long story short, directly comparing a Kyro to a TNT-2 is no more fair than comapring a 2X KyroII to a GeForce4 MX.

They have similar "ptifalls" when claiming they are "apples to apples" comparisons. NEITHER comparison is.

 

[demalion]

Snipping and addressing incomplete parts of my text doesn't go anywhere useful, especially as your following replies look as though you stopped reading at first and then only scanned the first sentence of subsequent paragraphs, in the process selectively skipping over almost all of the content of my post.. Less than useful, to say the least. Here are my replies...

The last and first posts that replied to me:

That makes even less sense than what I thought you were saying.

You are comparing the ratio of bandwidth to fillrate of an old 15 million transistor TBDR part as if that has anything to do with the bandwidth to fill rate ratio of all future TBDR card designs. That only thing that has to do with the decisions made in implementing that card. You see no inconsistency in applying that universally to all TBDRs while at the same time comparing it to an R300 or nv30 and pretending any earlier IMRs don't exist. Nor do you explain how this relates to eliminating overdraw penalties on using bandwidth and fillrate on an IMR (or, rather, you simply ignore the concern as far as I can see). Finally, you also ignore the impact of AA on the significance of your ratios.

...

The reply before that:

It answered the first sentences of two paragraphs of mine, and succeeded in ignoring a point made in the 2nd paragraph of text that applies to that entire post as a result:

Note both the transistor count/design complexity and the process are ignored by this evaluation.

Hmm...so a 130 million transistor chip on 0.13 micron costs the same as a ~110 million transistor 0.15 micron chip, running at the same clockspeed? Let's say they are on the same process (to your criteria for cost, its all the same) and running at the same clock speed, the 20 million transistor difference doesn't matter then? That seems to me an intrinsic and unavoidable flaw to your stipulation, which your answer did nothing to address (what was the point of these snippet replies in any case? all they did was avoid discussing the comment I repeat at the end of this post).

...

The reply before that:

I frame the question based on the assumption that he have no evidence that a TBDR with similar raw specificatoins would cost less than an IMR with similar raw specifications.

Interesting how your usage of cost changed.

The question I referred to was: "The goal is to build similary spec'd parts (cost). And then compare the resultant performance." Including that text of yours in your reply to my statement (since it is what my comment replied to) would illustrate that your new statement does not make sense (in the context of what you were actually saying). Go back and nest the quote in my quoted text and see how the post looks to you. If you don't have to reword your reply or include much more clarification, perhaps I can usefully reply to it.

...

Also...

Ignoring the central question I pose to you at the same time as responding in this fashion is something you know I find frustrating, why'd you do it? To repeat:

You justify this by saying we can't tell what design complexity would offer for a TBDR, so ignoring the possibility of any such benefit for a TBDR while also ignoring actual cost of the design complexity for increased efficiency in IMRs (which it so happens is not reflected in raw bandwidth and fillrate specs) is perfectly justified (because only raw bandwidth and fillrate specs matter for cost...). I simply don't think that makes sense.

This fits in with how you consider comparing a Kyro to a TNT (similar bandwidth, similar transistor counts) equally unfair to comparing a Kyro II to a GF4MX by increasing raw performance numbers (radically different transistor counts, because this doesn't matter to cost , and ignoring the possibility that a TBDR could be designed to use bandwidth differently with more complexity). It is a question I've asked repeatedly, that still applies even after your fresh start (the only thing that seemed to do was attempt to ignore the flaws pointed out in in your first replies).

 

[jb]

It's the same flaw that demalion tries to point out in my comparison. Kyro is a "newer" chip than the TNT2. What it boils down to is that the Kyro is a NEWER chip compared to the TNT2. So it can build in "stuff" for more efficiency because it was designed at a later date.

Hmmm what about a kyro vrs a V4 4500?
About the same time...about what 3 months apart? So that is "even"
The same hard ware configuration (no ddr, tnl, single tmu) ect so thats "even"
Spec was the kyro was slower on paper (clocked slower with lower fll rate).

Yet in the first link I provided (http://www.anandtech.com/video/showdoc.html?i=1253&p=9) it beat the V4 accross the board with lower specs! Is that good enough now

 

[Joe DeFuria]

damlion,

I give up. I can only repeat myself several times. You keep on talking about transitor count, AA, efficiency, etc.

ALL I'M TALKING ABOUT IS COST.

No, my usage of cost has not changed.

ASSUMPTION: SIMILARLY SPECD CARDS WILL HAVE SIMILAR COSTS.

THAT'S IT. HASN'T CHANGED.

It is a question I've asked repeatedly, that still applies even after your fresh start (the only thing that seemed to do was attempt to ignore the flaws pointed out in in your first replies).

Your posts are about as clear as mud. What question, exactly, have I not answered, to your satisfaction. Where is the question in this statement, that you claim I didnot address:

This fits in with how you consider comparing a Kyro to a TNT (similar bandwidth, similar transistor counts) equally unfair to comparing a Kyro II to a GF4MX by increasing raw performance numbers (radically different transistor counts, because this doesn't matter to cost , and ignoring the possibility that a TBDR could be designed to use bandwidth differently with more complexity).

ASK ME A DIRECT QUESTION.

 

[Ailuros]

Hopefully you won't take any offense, but when I skim through several pages added since I last logged in, just to read one or two posts and skip the rest, then there must be something wrong here.

Reality check: if PowerVR/ImgTec should release something later this year, then it will be at least two generations apart from what you're trying to analyze here. The K2 was a nice budget card for 2001 and that's about it.

 

[demalion]

Hmm...when mispellings of your name start to make it sound like a curse, perhaps the conversation has run its course for the night. We can continue tomorrow if you want.

damlion,

I give up. I can only repeat myself several times. You keep on talking about transitor count, AA, efficiency, etc.

ALL I'M TALKING ABOUT IS COST.

You propose that cost has nothing to do with the transistor count (or as Simon pointed out would be more accurate, chip real estate) or process size of the core.

You propose that instead it is directly linked to fill rate and bandwidth.

First, I say you are wrong.
Second, I've said multiple times why I think so.
Third, at the same time I've been saying so, I've pointed out the impact on TBDR design performance/cost ratio you circumvent in the process of making that unnecessary simplification.
You've replied to the text, but not answered it as far as I'm concerned. Your recent series of snipped replies seem, to me, to talk around every instance of it in my text and as a result went specifically nowhere.

No, my usage of cost has not changed.

ASSUMPTION: SIMILARLY SPECD CARDS WILL HAVE SIMILAR COSTS.

I see that you are considering cost synonymous with raw fillrate and bandwidth, I really do. I simply think you are wrong to do so. Further, I am saying that in the case of a particular phrasing (which I'm about to quote again), you invalidate this synonymity in a way that I cannot reconcile with what you were trying to address (that my description of your statement was incorrect).

In regard to this change in usage of the word, I point out that your established usage (that you repeat above) does not work with your statement:

I frame the question based on the assumption that he have no evidence that a TBDR with similar raw specificatoins would cost less than an IMR with similar raw specifications.

Specifically, you would be stating your assumption is that "we have no evidence that a TBDR with similar specs would have lesser specs than an IMR with similar specs".

To repeat myself, that statement does not make sense...I consider this fairly obvious, though you can simply correct me if you think I am in error, but please include a discussion of how cost is still synonymous with raw bandwidth and fillrate specs (one central point of our disagreement). Further...

THAT'S IT. HASN'T CHANGED.

I'm not trying to accuse you of a high crime, I am stating that your statement (beginning "I frame") is a distortion, facilitated by a change in usage of the word cost as well as the omission of the text of yours I replied to (which would not have allowed the distorted statement to stand). I proposed a simple remedy (go back and include what my statement was replying to for context), and said to you if you thought that reply still made sense to you without further clarification or rewording, I could perhaps go back and address it usefully.

Shall I arbitrarily try substituting words in the new phrase to remove the contradiction? I thought of several and I didn't find one that is either directly counter to the performance figures we have (and therefore fit my proposed description as does the text I was replying to when I made it), or absolutely equates "raw fillrate and bandwidth" with "performance" (and, therefore, is wrong, by the very principle of IMR efficiency having improved).

I consider this important because I don't think your established usage of what cost is (simply equivalent to fillrate and bandwidth) is valid for any level of this comparison, and your saying my statement was incorrect about what you were saying was only managed by changing your usage of cost to something else and omitting what you had said to illicit the reply.

It is a question I've asked repeatedly, that still applies even after your fresh start (the only thing that seemed to do was attempt to ignore the flaws pointed out in in your first replies).

Your posts are about as clear as mud. What question, exactly, have I not answered, to your satisfaction. Where is the question in this statement, that you claim I didnot address:

This fits in with how you consider comparing a Kyro to a TNT (similar bandwidth, similar transistor counts) equally unfair to comparing a Kyro II to a GF4MX by increasing raw performance numbers (radically different transistor counts, because this doesn't matter to cost , and ignoring the possibility that a TBDR could be designed to use bandwidth differently with more complexity).

What kind of dissembling is that, Joe!?!? Try the quote of my own text that I am referring to specifically in the latter text, specifically referred to with "This". Let me again repeat it in the form it appeared before that text:

Ignoring the central question I pose to you at the same time as responding in this fashion is something you know I find frustrating, why'd you do it? To repeat:

You justify this by saying we can't tell what design complexity would offer for a TBDR, so ignoring the possibility of any such benefit for a TBDR while also ignoring actual cost of the design complexity for increased efficiency in IMRs (which it so happens is not reflected in raw bandwidth and fillrate specs) is perfectly justified (because only raw bandwidth and fillrate specs matter for cost...). I simply don't think that makes sense.

Is it somehow unclear that this text is the question?

ASK ME A DIRECT QUESTION.

Well...the question seems to be: "How is that description of a flaw in your argument incorrect?" If more words are required, you could consider my question "I say that statement represents what you are doing, and is invalid...can you show me that it is either does not represent what you are doing, or is indeed valid?". The italic text is what I consider the important point of emphasis. I think if you'd quoted (read?) that text the question would have been clearer.

 

[KimB]

If tiling became dominant the pipeline would adapt before display lists became a problem, and you'd have both the bandwith for higher fillrate and no problem with increasing polygon counts ... so where is the problem?

I think you're going too much on faith here. I don't see a need for much more fillrate. I see tons of need for higher polycounts. I see deferred renderers increasing fillrate, but hurting polycount growth. Yes, it is always true that these are just engineering problems, problems that can be worked around, but I'd rather not have them at all.

Yes, but transforming the primitives multiple times is hardly a good option, particularly if vertex program lengths begin to get long.

As long as they are "Statistically rare" I dont care.

No, it won't be "statistically rare" if you're storing the scene buffer in world-space. Doing that would require at least two transforms of each vertex (one to bin the triangles, and one to render them).

 

[Joe DeFuria]

BTW, that "damlion" thing was a typo!

Anyway, this is why I'm having an exceedinly hard time with you:

You propose that cost has nothing to do with the transistor count

NO! I didn't propose any such thing!! Every time I make some statement, you seem to turn it around into something I didn't say. We'll go on forever like this.

OF COURSE transistor count has "something to do with cost."

But so does process size....and "what you do with those transistors", and yield, and a multitude of other things.

You propose that instead it is directly linked to fill rate and bandwidth.

Of course, FILL RATE has an impact on transistor cout. But you can't rely on transistor count as being reliable.

What's more expensive: A 500 Mhz chip with 50 million transistors, or a 750 Mhz chip with 35 million transistors?

Second, I've said multiple times why I think so.

You have given me no examples to support your position. IIRC, at least the "price" of TBDRs were in line with their RAW specifications. That at least lends support to my theory.

Third, at the same time I've been saying so, I've pointed out the impact on TBDR design performance/cost ratio you circumvent in the process of making that unnecessary simplification.

You completely miss the point again. We ALL KNOW THE THEORETICAL / TOUTED IMPACT OF TBDR DESIGN on PERFORMANCE / COST RATIO. THAT IS, GIVEN THE SAME EFFECTIVE BANDWIDTH/FILLRATE, THE TBDR DESIGN SHOULD BE CHEAPER. THIS SAYS NOTHING ABOUT TBDR DESIGN BEING CHEAPER WHEN COMPARING EQUIVALENT RAW SPECIFICATIONS.

I see that you are considering cost synonymous with raw fillrate and bandwidth, I really do. I simply think you are wrong to do so.

You haven't provided any reason to believe otherwise. Intead you talk about price / performance.

In regard to this change in usage of the word, I point out that your established usage (that you repeat above) does not work with your statement:

You can point at it all you like. I have not changed the "usage" of any word here.

Specifically, you would be stating your assumption is that "we have no evidence that a TBDR with similar specs would have lesser specs than an IMR with similar specs".

Uh....what?

No, I would be stating my assumption just like I said. That "we have no evidence that a TBDR with similar raw specificatoins would cost less than an IMR with similar raw specifications." Though you can take out the first redundant "similar raw specifications."

AGAIN, here is my assumption, with the redundanct removed. "we have no evidence that a TBDR would cost less than an IMR with similar raw specifications."

Where in this thread have I changed the meaning of anything in there?

To repeat myself, that statement does not make sense...

Right....YOUR statement makes no sense. Try reading MY statement again.

I'm not trying to accuse you of a high crime, I am stating that your statement (beginning "I frame") is a distortion, facilitated by a change in usage of the word cost...

Again, no where did I change usage of cost.

I consider this important because I don't think your established usage of what cost is (simply equivalent to fillrate and bandwidth) is valid for any level of this comparison, and your saying my statement was incorrect about what you were saying was only managed by changing your usage of cost to something else and omitting what you had said to illicit the reply.

Seriously, if you would STOP TRYING TO ANALYZE "who said what", and trying to get to the bottom of who clarified what in which way...blah..blah...and just focused a bit more on the CONTENT here, maybe this would be more frutiful, and less like shoving hot splints under my toe nails...

What kind of dissembling is that, Joe!?!? Try the quote of my own text that I am referring to specifically in the latter text, specifically referred to with "This". Let me again repeat it in the form it appeared before that text:

See what I mean? Gibberish.

Is it somehow unclear that this text is the question?

Entirely. You accuse me of "not answering questions." I expect you have a QUESTION for me to answer.

Well...the question seems to be: "How is that description of a flaw in your argument incorrect?"

Because I see no reason to believe that increasing the "actual cost of the design complexity for increased efficiency in IMRs" should be different than the "actual cost of the design complexity for increased efficieny in TBDRs."

I'm assuming they are on relatively even playing fields in that respect. Is that bad or unfair? If it takes X transistors in increase IMR efficiency Y%, should I not assume, given lack of evidence otherwise, that it also takes X transistors to increase TBDR by the same efficiecny Y%?

 

[Ailuros]

Hmm...when mispellings of your name start to make it sound like a curse, perhaps the conversation has run its course for the night.

Well raining on your parade wasn't actually my goal, but since you actually took it personal: good luck with the neverending substance free quote orgy.

 

[Tagrineth]

Kyro-II: 2.8 GB/Sec bandwidth available, 0.35 GPixel/sec fill rate.

In other words, despite whatever "bandwidth savings" is claimed to be saved, Kyro shipped as if it didn't have any, because it shipped with a similar bandwidth to pixel ratio as traditional IMRs. So why should we expect that a new deferred renderer will ship with a lower bandwidth per pixel ratio (which would reduce cost), compared to Kyro?

Well my last post was kinda wrong because I wasn't thinking straight, but I have a very simple logical explanation for this one:

They were already using SDR SDRAM (slow). The reason they went with a similar ratio is simply so they could synchronise the RAM clock to the core to reduce latency.

 

[demalion]

Hmm...when mispellings of your name start to make it sound like a curse, perhaps the conversation has run its course for the night.

Well raining on your parade wasn't actually my goal, but since you actually took it personal: good luck with the neverending substance free quote orgy.

Hmm...looking to pick a fight is not exactly rich in content, namely replying to a post that had nothing to do with you...

God, does everything have to turn into a put down contest? Do you think that contributed anything?

 

[Ailuros]

Then I apologize for the misunderstanding, since that comment followed my post and wasn't very clear where it was aiming. Besides I have a very vivid imagination and adding just one "F" in front of my username isn't exactly flattering LOL

Should have asked first; pardon.

 

[MfA]

If tiling became dominant the pipeline would adapt before display lists became a problem, and you'd have both the bandwith for higher fillrate and no problem with increasing polygon counts ... so where is the problem?

I think you're going too much on faith here. I don't see a need for much more fillrate. I see tons of need for higher polycounts. I see deferred renderers increasing fillrate, but hurting polycount growth. Yes, it is always true that these are just engineering problems, problems that can be worked around, but I'd rather not have them at all.

Not much more engineering than you would have to do to be able perform better occlusion culling ... with all those polygons artists will want to start to use densely occluded scenes for which standard host based occlusion culling works very poorly, if I see one more boxes connected by tunnels game from iD after DoomIII I am going to be very disappointed.

Yes, but transforming the primitives multiple times is hardly a good option, particularly if vertex program lengths begin to get long.

As long as they are "Statistically rare" I dont care.

No, it won't be "statistically rare" if you're storing the scene buffer in world-space. Doing that would require at least two transforms of each vertex (one to bin the triangles, and one to render them).

Whatever operation you have to perform on long thin poly's doesnt make them or their impact anymore significant if they are rare ... that they are expensive individually is inconsequential.

 

[DemoCoder]

I don't think we need higher polyrate at the moment, we need higher shader throughput. More ops/cycle. TBR is perfect for this, since you don't want to execute ops you don't have to.

It's not more vertices per scene, it's more complicated vertex and pixel shaders attached to each vertex and pixel.

Let's say you can do 300Mverts/sec. That's 5Mverts/scene. How many games today even get close to this number?

 

[demalion]

BTW, that "damlion" thing was a typo!

Sure it was.

Anyway, this is why I'm having an exceedinly hard time with you:

You propose that cost has nothing to do with the transistor count

NO! I didn't propose any such thing!! Every time I make some statement, you seem to turn it around into something I didn't say. We'll go on forever like this.

Joe, I've addressed this already. My problem is not the supposition that achieving fill rate increases cost, but that cost is equivalent to fill rate and bandwidth alone. Read what you go on to say right after this.

OF COURSE transistor count has "something to do with cost."

But so does process size....and "what you do with those transistors", and yield, and a multitude of other things.

Exactly what I stated...but...you persist in saying "cost" is only raw fillrate and bandwidth. Even ignoring direct quotes (I'll do that later) of what you've stated, that is how I interpret it when you discount the transistor count of the Kyro II and maintain that the performance with half the transistors and only increased fillrate and bandwidth is a valid comparison of "cost".

This assumption is central to every argument you've made concerning the expected performance/cost ratio of TBDRs, atleast as I see it.

Stepping back for a moment, my point is that I say we have indication that a TBDR can achieve equivalent performance for less cost and you respond this indication doesn't matter...based on the fill rate and bandwidth "cost" "equivalence" of your Kyro II comparison being valid.

You propose that instead it is directly linked to fill rate and bandwidth.

Of course, FILL RATE has an impact on transistor cout. But you can't rely on transistor count as being reliable.

What's more expensive: A 500 Mhz chip with 50 million transistors, or a 750 Mhz chip with 35 million transistors?

Umm...you also shouldn't ignore transistor count, nor process, either, as you do by trying to justify your Kyro II to GF 4 MX comparison and invalidate the Kyro and TNT2 comparison.

That doesn't answer the question, but neither does assuming fill rate is all that matters to cost. You are the one who stated an R300 and nv30 with the same fillrate would cost the same so blithely...

Second, I've said multiple times why I think so.

You have given me no examples to support your position. IIRC, at least the "price" of TBDRs were in line with their RAW specifications. That at least lends support to my theory.

Umm...to quote myself fully again:

You propose that instead it is directly linked to fill rate and bandwidth.

First, I say you are wrong.
Second, I've said multiple times why I think so.

You are saying I haven't supported why I think cost is not directly linked to fill rate and bandwidth alone? I think you just supported that above.

Third, at the same time I've been saying so, I've pointed out the impact on TBDR design performance/cost ratio you circumvent in the process of making that unnecessary simplification.

You completely miss the point again. We ALL KNOW THE THEORETICAL / TOUTED IMPACT OF TBDR DESIGN on PERFORMANCE / COST RATIO. THAT IS, GIVEN THE SAME EFFECTIVE BANDWIDTH/FILLRATE, THE TBDR DESIGN SHOULD BE CHEAPER. THIS SAYS NOTHING ABOUT TBDR DESIGN BEING CHEAPER WHEN COMPARING EQUIVALENT RAW SPECIFICATIONS.

Why do the raw specifications matter again? Does it matter more than effective bandwidth/fillrate for performance? If so, why is improving efficiency a goal for modern IMRs instead of saving transistors and increasing the clockability of a card? If you agree this indicates it is cheaper (it is in all caps, so I presume you mean it), this seems to point out that for the same cost it would have higher effective bandwidth/fillrate (performance).

It is when you substitute "cost" for "raw specifications" that you stop making sense.

If you take that back, do you take back your disagreement with:

I'll also point out that, taking Uttar's post as an example, the performance of parts with transistor counts of 12 million compared to 10.5 and then 15 million compared to 19 million does to me seem to indicate that the superiority of performance/production cost ratio for TBDR,

If so, it would have saved us time if you'd just said you'd changed your mind, as:

We ALL KNOW THE THEORETICAL / TOUTED IMPACT OF TBDR DESIGN on PERFORMANCE / COST RATIO. THAT IS, GIVEN THE SAME EFFECTIVE BANDWIDTH/FILLRATE, THE TBDR DESIGN SHOULD BE CHEAPER.

seems to be agreeing with it. Then again, an alternative explanation is you don't think effective fillrate/bandwidth indicates performance. Which I find strange as you automatically excluded HW T&L by saying the GF 4 MX and Kyro II comparison was justified (if geometry processing power doesn't matter, what else besides effective fillrate and bandwidth matter for performance?)

I see that you are considering cost synonymous with raw fillrate and bandwidth, I really do. I simply think you are wrong to do so.

You haven't provided any reason to believe otherwise. Intead you talk about price / performance.

OK, this conversation seems off track to me. Your phrases seem contradictory, acknowledging effective fillrate and bandwidth for less cost, and discounting talk about price/performance because of that. Maybe it is because I took a break to eat.

In regard to this change in usage of the word, I point out that your established usage (that you repeat above) does not work with your statement:

You can point at it all you like. I have not changed the "usage" of any word here.

Specifically, you would be stating your assumption is that "we have no evidence that a TBDR with similar specs would have lesser specs than an IMR with similar specs".

Uh....what?

No, I would be stating my assumption just like I said. That "we have no evidence that a TBDR with similar raw specificatoins would cost less than an IMR with similar raw specifications." Though you can take out the first redundant "similar raw specifications."

Well, I can't help thinking you are being deliberately obtuse. Let me point out why...

You maintain that "cost" is equivalent to "raw specifications", yes? Do I misquote or misunderstand "ASSUMPTION: SIMILARLY SPECD CARDS WILL HAVE SIMILAR COSTS." when the specs under discussion are raw fillrate and bandwidth? Let us try your phrase again:

"we have no evidence that a TBDR with similar raw specifications would cost less than an IMR with similar raw specifications." Yes, I'm aware that is the text you typed. My replacement of "cost" with "raw specifications" is because you said "cost" is equivalent to "the raw specifications".

But, perhaps that quote isn't representative, so let's go back a bit:

Because generally speaking, we all pretty much expect that cards with similar raw specs generally cost the same. 500 Mhz, 256 bit DDR-II costs "the same" no matter which chip it's paired up with. And the hope is, that a TBDR with the "same specs" (and therefore cost), would significantly outperform the competing IMR.

For cores, it is admitedly less black and white. But I see no reason so suspect anything other than as a best rough estimate, a TBDR core that puts out 800 MPix/sec (raw), "costs the same" as a 800MPix/sec IM core.

Can we agree on those assumptions? Before this is taken further, we have to agree on that.

I thought when I said, directly, that I could not agree with that, I made myself clear? You can't seem to decide whether you agree with that or not, and hence your use of "cost" shifts between one based on process, clockspeed, and complexity, and then to one where "equivalent raw fill rate and bandwidth means equivalent cost", and apparently you don't regard this as inconsistent. This leads to the above situation where you have no trouble stating a TBDR is cheaper than an IMR with the same equivalent fill rate, yet insist that we don't get better performance from a TBDR than from a IMR of the same cost (switcheroo!).

Perhaps we could clear this up and and move forward, since it reads to me you are deliberately abusing a change of definition to skirt my pointing out your being inconsistent. Though I have a lot of comments on the following text, like that "gibberish" comment in relation to a sentence rather selectively snipped, I doubt it would add anything to the conversation except even more repetition and noise.
If you think there is anything I really need to reply to, point it out.

I did read the entire post, btw, and I think your closing statement illustrates something I said before about you ignoring the difference between a TBDR and IMR. The TBDR is starting from high efficiency (efficiency the IMR is spending cost trying to approach)...you'd be spending the cost on a different type of performance enhancement. For example, the kind you you completey jump around by stipulating raw fillrate and bandwidth is the only criteria for cost. But, I repeat myself...enough of that.

 

[demalion]

Then I apologize for the misunderstanding, since that comment followed my post and wasn't very clear where it was aiming. Besides I have a very vivid imagination and adding just one "F" in front of my username isn't exactly flattering LOL

Should have asked first; pardon.

Bah, if you can LOL about it and apologize, you achieve 100% forgiveness efficiency. Feel free to carry on your criticism of these long posts of mine with a clean slate.

 

[KimB]

I don't think we need higher polyrate at the moment, we need higher shader throughput. More ops/cycle. TBR is perfect for this, since you don't want to execute ops you don't have to.

The TBR is no better with not executing unecessary ops if the algorithm uses an initial z-only pass, which may be necessary for global shadowing anyway. I think that once the world sees DOOM3 in its full glory, global shadowing will become the norm.

And while I agree that we definitely do need higher shader input, I see no reason why a tiler will be fundamentally better at this than an IMR. Furthermore, I see no reason why more triangles cannot be pursued in addition to more complex shading.

 

[DemoCoder]

Because a TBR can fill Z/stencil faster than an IMR.