PlayStation III Architecture

[Vince]

I am sure they will choose the best option... maybe by PS3's launch the 65 nm process is going to be mature enough...

I'm sure Marco or Ben would be a good person to ask, but when you design a chip, like the Cell based architecture specifically for PS3, you design with specific libraries and thus a target process in mind.

They don't sit down and say, "Hey, 65-micron is working, lets shift everything to that." I doubt there is any form of cohesion between the 90 and 65nm libraries - it's certainly not a simple reductionist method like the move from 0.25um to 0.22um was IIRC. It's more or less a total redesign AFAIK.

EDIT: Besides, shouldn't they be close to producing a functional netlist soon? How long does the back-end work take on a CPU such as this? I can't imagine the synthesis, place/routing being easy on a chip that could potentially have upwards of a 100M gates.

 

[Panajev2001a]

They don't sit down and say, "Hey, 65-micron is working, lets shift everything to that." I doubt there is any form of cohesion between the 90 and 65nm libraries - it's certainly not a simple reductionist method like the move from 0.25um to 0.22um was IIRC. It's more or less a total redesign AFAIK.

I know, but if they have said ( this decision might have happened a good while ago, before the announcement of the 65 nm process ) "hey the 65 nm process is having TERRIBLE yelds" then maybe they won't PUSH the 65 nm as the best choice for the PS3 chip and they will plan the migration when the process is more mature..

And yes I do understand that die-shrink is a complex process which involves more than "let's make the chip smaller" but they have done and will do tests to see the viability of 65 nm technology ( for all we know those tests might have already been performed and the result WAS that by 2005 they foresee good yelds with 65 nm technology... ) and when it will have good hopes of high yelds then the redesign process for a die shrink will start full force...

 

[V3]

Thanks Vince

Its that, I find it hard to belive they will get the 65nm process ready for mass production in 2004, where as 0.1u is more believable. Like Pana said 65nm will reduce cost, but yield could be problematic.

But if they indeed target 65nm process from the beginning, than the current spec for PS3 is rather conservative.

EDIT: Besides, shouldn't they be close to producing a functional netlist soon? How long does the back-end work take on a CPU such as this? I can't imagine the synthesis, place/routing being easy on a chip that could potentially have upwards of a 100M gates.

Its modular, so it shouldn't be as hard.

 

[Panajev2001a]

But if they indeed target 65nm process from the beginning, than the current spec for PS3 is rather conservative.

We also need the costs for Broadband Engine + Visualizer to be low ( and the current specs show them to be quite powerful already, but I know they bwill be fine tuned more ) so that for a normal console like price they can put a good amount of fast external RAM and do a good job with PS2/PSX backward compatibility... and let's not forget Blu-Ray: PS3 needs a good new medium that looks to the future ( dragging plain DVD would be bad as Xbox 2 would get Blu-Ray and use it as a quite good marketing tool )... PS3 should have Blu-Ray, it is a console after all made to last 4-5 years...

 

[Peppermonkey]

Isn't Blu-Ray a recordable media, wouldn't this add to the threat of piracy?

I'm not so sure if even the Xbox 2 is going to get Blu-Ray. I'm hoping that they find something similar, but not exactly the same, so as to keep piracy down for a longer time, so I don't have to spend $70 for the next-gen games.

The Gamecube has yet to get piracy AFAIK, and I certainly doubt that it's going to have a problem with it any time soon. I certainly think that the lack of piracy on the GC is due to the fact that Nintendo uses Mini-DVDs.

 

[Panajev2001a]

Piracy can be controlled, but not stopped totally... PS2 was supposed to be secure and Xbox too ( they touted it ), but once the request for pirated software raised, cracking begun and succeeded...


Blu-Ray offers a lot of ben efits with the huge space offered ( 25+ GB ) and the re-writability... no need of HD or memory cards ( easy game upgrading, etc... ), etc...

 

[Vince]

Its that, I find it hard to belive they will get the 65nm process ready for mass production in 2004, where as 0.1u is more believable. Like Pana said 65nm will reduce cost, but yield could be problematic.

I did some asking today and found that Intel is going to begin mass production on their 65nm process in 2005.

As far as my friend know of, IBM doesn't even have a 100nm production CMOS process - he said they already started first production of 90nm parts on their new 300mm wafers with SOI, Cu, ect.

Besides, production on any PS3 part is still 2 years away. SCE has already been making 130nm Graphic Synthesizers for like 6 months at Nagasaki IIRC, a Combined EE+GS at 130 or 90nm is inevitable.

You really think they're going to use 0.10um in 2004? I call that sheer ignorance or stupidity - with all due respect.

Its modular, so it shouldn't be as hard.

What does that have to do with the physical layout of the chip? From what I heard today, the mask set needs to be completed roughly a year ahead of mass production for a modern CPU - Toshiba/Sony announced 65nm last month. A good year and a half (being conservative) would allow for a late 2004 intoduction - I don't anticipate this... but atleast this is grounded speculation, unlike what you're stating.

 

[Panajev2001a]

As far as my friend know of, IBM doesn't even have a 100nm production CMOS process

and your friend is not well informed I have to say... no offense to you or to him ( seriously )...

http://www-3.ibm.com/chips/news/2001/0312_ibm-sony.html

Tokyo - March 12, 2001

IBM Corporation (IBM) and Sony Computer Entertainment Inc. (SCEI) today announced an agreement regarding the license of 0.10 micron SOI* Process Technology (CMOS 10S) for use in future broadband processors.

In the broadband era, processors will need to handle huge amounts of data and program to and from multiple sources in real-time. To achieve the larger scale integration of processors required, a high level of process technology is imperative.

SCEI has agreed to license from IBM the latest process technology for the fabrication of 0.10 micron design rules. Through the license, SCEI will acquire the most-advanced production technology, from which SCEI plans to build and enhance its process technology expertise.

SCE has already been making 130nm Graphic Synthesizers for like 6 months at Nagasaki IIRC, a Combined EE+GS at 130 or 90nm is inevitable.

The last thing I heard from a member of Team Nishi ( working at Sony, some members are well situated in software R&D positions IIRC ) was that Sony already has worked on a single die with EE and GS... an EE+GS combo in .13u IIRC ( practically comparable to the original EE that shipped in launch PS2's) in size...

What does that have to do with the physical layout of the chip? From what I heard today, the mask set needs to be completed roughly a year ahead of mass production for a modern CPU - Toshiba/Sony announced 65nm last month. A good year and a half (being conservative) would allow for a late 2004 intoduction

That is a good point Vince and I am not saying that they will not use 65 nm for launch PS3 chips...

You say by that time the 0.10um SOI process will be 2 years old... well I do not see major MPUs of even similar caliber shipping ALREADY with less than o.13u and the first 90nm Intel part is not out yet ( Prescott should come out in some months )... Knowing that CELL should go into mass prooduction by early 2004 ( at the latest ) you gotta ask yourself "is 65 nm ready by early 2004 ? With what kind of yelds ?"

I am not saying that by 2005 Sony will not have started or completed the transition to 65 nm ( assuming they're not pointing to 65 nm as target process in the first place ), I am just saying "do not be surprised if in several of Japanese launch PS3 you find 0.10u SOI cu parts

 

[Vince]

and your friend is not well informed I have to say... no offense to you or to him ( seriously )...

Heh.. no offense taken... but I'd watch whatcha say because not only is he a smart guy (and my buddy), but from what he said, and what I've seen IBM isn't actively producing a 100ns process. From what he was saying, and I've read in the past, is that dating back to 2000/2001 many were looking to 0.10, 0.07, 0.05um and other odd sizes. It seems production is now based around 0.09, 0.065, 0.045um.

I happen to believe him when you do a search and find the origional article from 2001 which states:

TOKYO — Toshiba Semiconductor Co. and Sony Corp. have launched a three-year R&D effort to establish 0.10-micron manufacturing technologies by September 2002 and 0.07-micron technologies by March 2004.

http://www.siliconstrategies.com/story/OEG20010518S0029

And then fast-forward to the present day and many of the expected difficulties of finer lithography have been solved or worked around (point 1 barrier anyone) and they're stating the following:

TOKYO--Enabling the shift towards “ubiquitous computing,â€￾ Japan's Toshiba Corp. and Sony Corp. late Monday announced the world's first 65-nm CMOS process technology for embedded memories

http://www.siliconstrategies.com/story/OEG20021202S0091

This just seems obvious to me.

You say by that time the 0.10um SOI process will be 2 years old... well I do not see major MPUs of even similar caliber shipping ALREADY with less than 0.13u and the first 90nm Intel part is not out yet ( Prescott should come out in some months )

As far as the fabrication process and libraries, Intel's well past 90nm. IIRC from eetimes, their almost done with 65nm and are beginning work on 45nm to be introduced in 2006/7.

Knowing that CELL should go into mass prooduction by early 2004 ( at the latest ) you gotta ask yourself "is 65 nm ready by early 2004 ? With what kind of yelds ?"

2005, means production in Q4 2004. 65nm libraries are done, Toshiba has asked Sony for money to build a new Fab

I am not saying that by 2005 Sony will not have started or completed the transition to 65 nm ( assuming they're not pointing to 65 nm as target process in the first place ), I am just saying "do not be surprised if in several of Japanese launch PS3 you find 0.10u SOI cu parts

See, I totally disagree. Not only is nobody activly producing 100nm or devoting public fab space to it, but Toshiba is already gearing up for sub-90ns and the fab they want Sony to contribute to isn't going to be based around a process thats old, feable, and was never followed-up on. Toshiba and Sony liecensed probobly liecensed the .1um SOI process so they could utilize IBM's supurb SOI, strained-silicon, ect in their own future processes.

For example, Toshiba's new 300mm Fab in Oita that they want Sony to help fund:

The new production line at Oita Operations will mass-produce cutting-edge System LSIs for broadband network applications, using the company's world-leading embedded DRAM process technology. This advanced facility, which is expected to adopt 45-nanometer process technology in the future, will assure Toshiba retain its leadership in the System LSI business. Construction will start in FY2003 and mass production is scheduled to start in FY2004.

http://www.toshiba.co.jp/about/press/2002_12/pr1301.htm

PS. I need to get movin' into the shower as I'm already late as usual, so don't expect a reply from me untill tomorrow... I didn't leave the argument.. yet

 

[JF_Aidan_Pryde]

Is somebody going to tell me what LSI stands for or let me read it everyday on EEtimes without a frigg'in clue?

 

[KnightBreed]

Is somebody going to tell me what LSI stands for or let me read it everyday on EEtimes without a frigg'in clue?

Large Scale Integration

http://www.lsilogic.com/about/stw/acronym.htm

 

[Panajev2001a]

Before I touch again the current topic ( manufacturing process [I have a preview for you though of my reply: good and valid arguments, you do have something in your hands it seems..., but watch out I am the kind of opponent that when he loses an argument he takes the opponents' arms off... j/k, aside the Star Wars reference I am liking this argument as you're trying to make a point prooceeding step by step giving me rational points and I like it ] )... I have a point I want to touch again ( please read the whole message )...

The APUs...

Are they micro-coded or not ? Can they be also micro-coded ( cna they run micro-code ?

The first question is dependent on the second one because the answer would be "it depends".

The second question would be answered by me with a "Yes" for various reasons...

The first is one of the more specific hints the patent gives us:

[0144] In lieu of an absolute timer to establish coordination among the APUs, the PU, or one or more designated APUs, can analyze the particular instructions or microcode being executed by an APU in processing an apulet for problems in the coordination of the APUs' parallel processing created by enhanced or different operating speeds.

Why am I thinking about micro-code ?

Well we know some things:

1) a software cell can run on any processor in the network

2) the APUs share a common ISA

3) the APU are "preferrably" SIMD based ( Integer and FP [1 FMAC and 1 FDIV in each of the FP Unit in the APU ?] )

4) the number of FP units in the APU can change to a higher and also lower value than he regular 4 FP Units/APU ( same is worth for the integer side )...

I have two ideas regarding this ( let's think about runnign a 4-way parallel MADD [SIMD... oh and btw, who knows if in the ISA of the APU there are not scalar instructions like it happened with SSE 1-2] ):

1.) First the problem of running the said 4-way parallel MADD on APUs with fewer FP Units than the standard 4 FP Units/s as the current specs prefer...

2.) Second the problem of running that instruction in APUs with more than 4 FP Units...

First problem ( 1.) ):

the APU that receives such instruction would have a micro-code that would execute said instruction even with a smaller number of FP Units than expected... Looping back might be key to this...



Second problem ( 2.) ):

This could be solved by adding NOPs to the instruction stream since this is not an instruction designed specifically to run on slower machines ( processing power wise ) or maybe the PU might send a bigger workload to the APU... after all the software cell is processed by the APUs accorind to how the PU is instructing them to...

The PU schedules and orchestrates the processing of data and applications by the APUs.

Or maybe the APU can issue a new instruction with the free FP Units, but if the supposed 5th FP Unit can work independently from the other 4 why cannot the other 4 work independently from each other ?



Sorry If I am being a bit messy with making my argument, but I am quite sleepy ( still wanted to post, have thought about this all evening )...


Mine is an implementation issue... we have APUs that are generally SIMD processor ( for both Integer and Data ) and we say this:

Since all computing resources have the same basic structure and employ the same ISA, the particular resource performing this processing can be located anywhere on the network and dynamically assigned.

But it is also said that an APU can have more than 4 FP or Integer Units or less than 4 depending on processing needs... still we keep the same ISA...

how do you process a 4-way SIMD operation like a vector MADD if you are allowed to have a variable amount of Execution Units ?


This is the issue... above I tried to give some quick and dirty "possible" implementation decisions ( although I apologize for maybe the poor wording ), but there is surely more ground to cover on this...




In a still related topic, don't you love the software cells structure and the incorporation of routing information in the header ( and having both data and instructions )...

[0121] The structure of software cells 102 is illustrated in FIG. 23. As shown in this figure, a software cell, e.g., software cell 2302, contains routing information section 2304 and body 2306. The information contained in routing information section 2304 is dependent upon the protocol of network 104. Routing information section 2304 contains header 2308, destination ID 2310, source ID 2312 and reply ID 2314.

each of these ID's contains a network address...

uhm... destination ID could be Destination Address, source ID could be Source Address and reply ID ( from what I read ) could be the next hop, as we read here:

The destination ID includes a network address. Under the TCP/IP protocol, e.g., the network address is an Internet protocol (IP) address. Destination ID 2310 further includes the identity of the PE and APU to which the cell should be transmitted for processing. Source ID 2314 contains a network address and identifies the PE and APU from which the cell originated to enable the destination PE and APU to obtain additional information regarding the cell if necessary. Reply ID 2314 contains a network address and identifies the PE and APU to which queries regarding the cell, and the result of processing of the cell, should be directed.

Implementing a routing protocol like RIPng ( no sense using RIPv2 as IPv4 based and RIPng should be backwards compatible and most RIPv2 routers will still process a RIPng message or try to I am talking based on experience... plus the RIP specs in that RIPv2 FRC are not clear on the RIP version 3 or greater subject ) or OSPF for IPv6 could be implemented quite nicely with this software cell structure...

In the data portion we can store the rest of the header including TCP/UDP etc...

"Wait" you will say "what about layer 2 where do you put the MAC address info ?" Well it is not an uncommon practice in IPv6 to base the 128 bits address of a network interface on the MAC address, using the MAC address as part of the IPv6 address...

We could encode layer 2 and layer 3 informations in simple IPv6 addresses...

I do not know yet ( maybe some of the images of the patent will give me a better understanding ), but I do think that the network address used in those "ID's" is effectively an IPv6 address: good for a forward lookin g architecture like CELL and that makes sense judging by a partnership Sony started with CISCO related to some IPv6 and IPv4 work ( including a hybrid protocol, IIRC)...

128 bits addresses would fit quite nicely in those 128 bits registers the APUs have

This architecture is indeed flexible... since we already have tons of software routers around why not choosing one that uses the "CELL architecture" there is basiclaly support in HW

 

[Panajev2001a]

Heh.. no offense taken... but I'd watch whatcha say because not only is he a smart guy (and my buddy), but from what he said, and what I've seen IBM isn't actively producing a 100ns process. From what he was saying, and I've read in the past, is that dating back to 2000/2001 many were looking to 0.10, 0.07, 0.05um and other odd sizes. It seems production is now based around 0.09, 0.065, 0.045um.

I happen to believe him when you do a search and find the origional article from 2001 which states:

TOKYO — Toshiba Semiconductor Co. and Sony Corp. have launched a three-year R&D effort to establish 0.10-micron manufacturing technologies by September 2002 and 0.07-micron technologies by March 2004.

http://www.siliconstrategies.com/story/OEG20010518S0029

And then fast-forward to the present day and many of the expected difficulties of finer lithography have been solved or worked around (point 1 barrier anyone) and they're stating the following:

TOKYO--Enabling the shift towards “ubiquitous computing,â€￾ Japan's Toshiba Corp. and Sony Corp. late Monday announced the world's first 65-nm CMOS process technology for embedded memories

http://www.siliconstrategies.com/story/OEG20021202S0091

This just seems obvious to me.

Do not worry, I would not flame you or your friend unless wrongly attacked first and neither of you seem like the type ( you do have some temper hehe )... plus you make sense...

I didn't know for once that Sony ( I must have missed that announcement ) and Toshiba were working towards 0.10um and 70nm and had 2002 and 2004 as respective targets I will admit this... and that line about "ubiquitous computing" sounds a lot like the CELL model to me

I can see the picture better now Vince thanks, I can see better the progression from initial research and the 65 nm process announcement and I can see where IBM tech might have helped...

As far as the fabrication process and libraries, Intel's well past 90nm. IIRC from eetimes, their almost done with 65nm and are beginning work on 45nm to be introduced in 2006/7.

True, but I was thinking in temrs of actual manufacturing...

2005, means production in Q4 2004. 65nm libraries are done, Toshiba has asked Sony for money to build a new Fab

See, I totally disagree. Not only is nobody activly producing 100nm or devoting public fab space to it, but Toshiba is already gearing up for sub-90ns and the fab they want Sony to contribute to isn't going to be based around a process thats old, feable, and was never followed-up on. Toshiba and Sony liecensed probobly liecensed the .1um SOI process so they could utilize IBM's supurb SOI, strained-silicon, ect in their own future processes.

For example, Toshiba's new 300mm Fab in Oita that they want Sony to help fund:

The new production line at Oita Operations will mass-produce cutting-edge System LSIs for broadband network applications, using the company's world-leading embedded DRAM process technology. This advanced facility, which is expected to adopt 45-nanometer process technology in the future, will assure Toshiba retain its leadership in the System LSI business. Construction will start in FY2003 and mass production is scheduled to start in FY2004.

http://www.toshiba.co.jp/about/press/2002_12/pr1301.htm

The news about the new fab with 65 nm technology Toshiba is planning is interesting as such a technology would allow processors such as the Broadband Engine and the Visuallizer as we have seen in the patents at reasonable costs... I am wondering if they could maybe shrink the EE+GS combo to .65 nm and pack on the same chip also the Direct RDRAM, the I/O CPU ( and related RAM ) and the SPU2 ( and related RAM ) ?... Maybe they could use this PS2-on-a-chip as PS3's new I/O ASIC...

I do see now why Sony and Toshiba licensed the .10u SOI cu process from IBM and why they got so close to IBM's special manufacturing secrets...

The PR about the license of that process is from March 2001, but approaching IBM regarding that tech might have started earlier as Sony and Toshiba were trying to work on their new manufacturing process that led them to the new 65 nm process: Sony might have found in IBM tech what they needed to push the development much further... IBM' technology might have been the factor that got us in late 2002-early 2003 the new 65 nm process...

After all a good year ( and more ) passed between the two announcements...

PS. I need to get movin' into the shower as I'm already late as usual, so don't expect a reply from me untill tomorrow... I didn't leave the argument.. yet

"late as usual"... you remind me of myself

 

[Panajev2001a]

buuuump

 

[V3]

You really think they're going to use 0.10um in 2004? I call that sheer ignorance or stupidity - with all due respect.

0.1 is certainly going to be ready for mass production in 2004. The other processes is still hoping if all goes well for 2004.

 

[V3]

Are they micro-coded or not ? Can they be also micro-coded ( can they run micro-code ?

My guess at the moment would be yes and yes.

Or maybe the APU can issue a new instruction with the free FP Units, but if the supposed 5th FP Unit can work independently from the other 4 why cannot the other 4 work independently from each other ?

Do you mean the APU can break down the single instruction that was issued by PU into several instruction to optimised the process according to resources available ?

how do you process a 4-way SIMD operation like a vector MADD if you are allowed to have a variable amount of Execution Units ?

The PU should still schedules and orchestrates its given APUs. So my guess the PU would have some knowledge of what its APUs are capable of.

I do not know yet ( maybe some of the images of the patent will give me a better understanding ), but I do think that the network address used in those "ID's" is effectively an IPv6 address: good for a forward lookin g architecture like CELL and that makes sense judging by a partnership Sony started with CISCO related to some IPv6 and IPv4 work ( including a hybrid protocol, IIRC)...

Hehe I think that's a pretty good guess

 

[Vince]

0.1 is certainly going to be ready for mass production in 2004. The other processes is still hoping if all goes well for 2004.

I thought I made this clear Bud; nobody is mass manufacturing in 100nm. None.

IBM's Fishkill is ramping 90nm SOI, Toshiba's Oita is at 90nm aswell. It's a minimum of 90nm as Toshiba is already at 90nm production* with 65nm looking very, very likely. Didn't you read the Sony/Toshiba roadmap for 70nm in 2004 - which has now shifted to 65nm?

* http://www.infoworld.com/articles/hn/xml/03/01/13/030113hnnanometer,txt.xml?s=IDGNS

 

[Panajev2001a]

Vince,


I have one thing to say buddy...



man you take LONG showers


seriosuly, thanks for the links... I am getting more interested into knowing the actual chances of sub 100nm processes being used for PS3 and it seems I was wrong expecting 0.10um in 2004/2005 ( well if they have plants NOW at 90 nm and they say that they got their new 65 nm process almost ready [well the factories are not producing 65 nm chip as of yet ]... it must mean that the yelds on those are pretty good )... well if they can produce PS3 chips at 65 nm better for them and for us, the customers...


still... what do you think about the other post I made ? ( please take your time answering )

 

[Panajev2001a]

again... reading that link... well if they cna ship 90 nm chips now... building a new fab, knowing that they have completed the libraries for 65 nm it seems unlikely that they will use 100 nm process for the new fab...

1 year and a half... 65 nm process... I wonder if they pushed for the 65 nm process for CELL due to its size and transistors' complexity... which must be high...

65 nm vs 90 nm... a parity of good yelds, 60 nm should mean considerably lower chips' cost...


I do hope that they can use 65 nm for CELL as it would proove that Sony, IBM and Toshiba are not behind Intel ( not considerably )... yes I am one of the guys that hopes to see CELL used everywhere... and if they even try to do that, having a state of the art manufacturing process is fundamental...


I wonder if they can do a PS2-on-a-chip at sub 90 nm... do you think it could fit ? ( well you could take the GS off since that part would be emulated on the Visualizer...

The PSX CPU could be taken off... but I'd say no... reason is that much of the TCP/IP stack ( in online games ) runs on the I/O CPU and the I/O CPU can be used to help the SPU2 ( and has been probably used )...

what I say is... emulate PSX's and PS2 GPUs on the Visualizer... this way you save the GS's 4 MB of e-DRAM and you can make this PS2-on-a-chip even smaller... and maybe even use it as I/O + Sound DSP

 

[V3]

I thought I made this clear Bud; nobody is mass manufacturing in 100nm. None.

Chill out man, I refer to 90nm as 0.1 tech for now.

IBM's Fishkill is ramping 90nm SOI, Toshiba's Oita is at 90nm aswell. It's a minimum of 90nm as Toshiba is already at 90nm production* with 65nm looking very, very likely. Didn't you read the Sony/Toshiba roadmap for 70nm in 2004 - which has now shifted to 65nm?

Yes Even Intel are on 90nm and beyond. But, like I said before that's if everything goes to plan for 65nm in 2004. Anyway the spec on that patent seems to target, 0.1 tech. But things are modular so to increase specs is probably easier, than before.