Over the next 3 years how will Graphics chips evolve?

[g__day]

Simple question, I'd love to hear your views.

Whilst all attention will shortly be focused on GeForce FX and ATi's counter moves, I ponder what major features will be introduced as graphics crads become alot faster, more programmable and hopefully easier to use.

Given the knowledge base here, what would you hope or like to see come out in the next 3-4 generations of hardware? Who can do a good look over the horizon and forsee what will come and whether its one, two or three generations away?

Thanks in anticipation!

 

[Hellbinder]

They will be faster and do more stuff better.

 

[Jamm0r]

You're a genius Hellbinder

 

[Millennium]

I bet they will be more powerful

 

[arjan de lumens]

Obviously, stuff like more fillrate/triangle rate/shader execution rate/memory bandwidth and better AA/aniso, that sort of stuff. In 3 years, I'd estimate about 4-8x the performance of today's chips at any given price level.

As for new features:

• More tessellation methods - in particular variants of subdivision surfaces (fixed-function, I guess - using a programmable unit to do tessellation makes it too hard to exploit the parallellism possible to achieve at tessellation time). Probably a new shader stage to process control meshes before tessellation, in addition to vertex shaders afterwards.
• Vertex/pixel/control-mesh shader instruction sets will converge and become ever richer in features and flexibility, until they can be used as general-purpose CPUs in their own right (at which time the GPU as a whole will look a lot like the PS3 CELL architecture)
• Scene graph APIs, and the hardware support/programmability to process entire scene graphs on the GPU side.

 

[mr]

SA made a great post concerning the outlook of 3d graphics for the coming years.

http://www.beyond3d.com/forum/viewtopic.php?t=1092&highlight=

 

[3dcgi]

I think more companies will use a 3dlabs type approach with generic processing units that can be allocated to geometry or pixel processing based on the application. 3dlabs currently has this flexibility to a limited extent.

 

[archie4oz]

Vertex/pixel/control-mesh shader instruction sets will converge and become ever richer in features and flexibility, until they can be used as general-purpose CPUs in their own right

Good'ole Sutherland wheel of reincarnation...

 

[Ostsol]

Hardware support for more higher-order surfaces, like NURBS, would be interesting to see. It'd also be nice to see real, dynamic displacement mapping. From what I've heard, the NV30 and R300 merely tesselate the surface and store the new vertices in memory, while the Parhelia tesslates the surface on the fly.

 

[Bigus Dickus]

I'd really like to see depth of field, but it sounds like a difficult feature to implement in real time.

And what about 3D rendering? I've never looked at the "3D glasses" before. Do they actually give a true 3D depth perception, or just fake it somehow?

I'd like to see a card that can render each frame twice from slightly different perspectives (that part shouldn't be hard should it, so long as the card is fast enough?) for left and right eye positions. Or is that what the glasses do when supported by the correct drivers?

Combined with depth of field, that could be nice.

 

[jjayb]

Just make a card that plugs directly into my brain already.
I'm tired of staring at my dinky 19'' monitors. I want my head filled with visuals.

 

[mr]

Stereo3D

slightly OT

Hi Bigus Dickus,

Over at Guru3D they got a nice little overview of stereoscopic rendering.
http://www.guru3d.com/stereo/general/
Make sure to check out the links at the end of the article.

I want one of those:
http://www.dresden3d.com/default.de.htm
8)

 

[Dave B(TotalVR)]

I think that holographic monitor support will be something that makes its way into GPU's before that 3 years is up. We already have the technology and lets face it, a truly 3D monitor is somewhat appealing to me at least.

 

[Basic]

I think that holographic monitor support will be something that makes its way into GPU's before that 3 years is up. We already have the technology and lets face it, a truly 3D monitor is somewhat appealing to me at least.

Any links to holographic monitor stuff?

 

[JF_Aidan_Pryde]

It surprises me that no one knows much about holographics there. I guess it's quite different from the conventional 3D theory and silicon engineering but rather to do with optics.

Can anyone explain what is the bottleneck in producing a consumer 3D holographic monitor?

 

[mboeller]

instead of an "lowspeed" design with many pipelines, we could see an highspeed design with only 4pipelines; cause with an high polygoncount more than 8 (or 4) pipelines are inefficient. So it could very well be, that the next gen 3D chips work at <=2GHz; 4Pipeline Design with only one Vertex-Shader (=500Mio Poly/sec) and 256bit DDRII @ 500MHz with only 60-75Mio Transistors. This design would be as bandwidth constrained as an NV25.

 

[arjan de lumens]

With high polygon counts you could set up the renderer pipelines in groups of, say, 4, and then allow each group to work on a different polygon.

Higher clock speeds means higher latency, measured in number of clock cycles, so you need to keep more pixels in flight per pipeline to keep up the efficiency. The result is that many of the buffers (like texture mapper queues, shader register file instances, etc) needed for efficient operation must be made larger, proportionally to the clock speed. Also, the number of pipeline steps in each pipeline must be increased, in sum resulting in larger power consumption per pixel rendered. Given the additional pipeline steps and the enlarged buffers, the chip space savings of doing few high clock speed pipelines rather than many low-speed pipes are smaller than one might initially think.

Also, circuit design generally gets slower and more difficult the higher clock speeds you want - stuff like automated circuit generation/synthesis/place&route tools generally aren't very useful at >2GHz - pretty much everything has to be done at hand at such clock rates, increasing development time dramatically.

 

[Arun]

Please note that the following is a *wish* list. I didn't feel like typing "probably" and "hopefully" everywhere.
I think most of it is possible and logical, but maybe I'm way too optimist. Or simply illogical. Or whatever.

First of all, we're going to move to nearly identical PS & VS. That means some of the calculation units will be dynamically allocated, so that "bottlenecks" are a lot less important. You won't be required to balance PS&VS effects on triangles as much as before.
The hardware will be able to determine how to do the best balance of both, so that a 1000 instructions PS with a 25 instructions VS doesn't make the PS the bottleneck.
I believe the GFFX ( and some 3DLabs P10 VS ) is already a step in that direction, with its 32 FP calculators it dynamically allocates ( however, so little is know about it that I might be 100% wrong on that. Any info about how it really works? )
This will allow nearly every transistor to used at every single time, even in what seems to be a very unoptimal case.
And it'll also help those poor programmers, because they'll barely have to do any bottleneck optimization work once it becomes a standard.

Secondly, we'll get programmable primitive processors. They'll probably be before the VS. So, basically, it'll be just like TruForm, but programmable. This will slightly help memory bandwidth, because less vertices have to be sent from GPU memory. But then again, that probably barely is between 5% and 10% of memory bandwidth right now, so it wouldn't change much if done today. The main advantage is allowing next-gen polygon counts, which require a lot more.
But we'll probably get more fixed tessellation methods before getting a truly programmable one.

As for bandwidth-saving techniques... Deferred rendering, of course. Series 5 might be interesting for that. There's not much more that can be done after Color Compression.


Uttar

 

[Dave Baumann]

I believe the GFFX ( and some 3DLabs P10 VS ) is already a step in that direction, with its 32 FP calculators it dynamically allocates ( however, so little is know about it that I might be 100% wrong on that. Any info about how it really works? )

WTF are you talking about?

 

[Neeyik]

I think what he means Dave is that graphics chips of the future will have identical vertex and pixel ALUs (along with identical shader routines/language/instructions/fluffy bits), so that the instruction workload can be better shared out if cases where you have either a shed load of vertex work and little pixel work, and vice versa.