nonamer said:
This post is nonsensical. Ever heard of a GPU?
No, YOUR post is nonsensical. When discussing family sedans on a forum, do you often feel an urge to interject with words similar to, 'this post is nonsensical. Ever heard of a tractor?'
You don't think PS3 will have a GPU as well or something? We were discussing CPUs here, not GPUs.
Before accusing others of being nonsensical, try and make sense yourself first.
Saem said:
I see you didn't comprehend what I'm saying.
Uh, excuse me, but
... Yes, I did.
I'm talking about MPUs. Not a specific one, just MPUs, in particular, high performance parts.
Yes? So what. Like I said, you can't take one idea, or a concept of an idea ('MPUs in general') and apply it to something specific to try and judge the general clock speed potential/performance of that specific part.
Reasoning that Cell is A: brainy, and B: brainy parts usually don't live up to its potential, and hence: C, Cell won't live up to its potential is stretching things too far since we know nothing of the specifics of Cell yet, including targetted clock speed. All we got is that patent which states the chip would have a 'preferred' performance of 1Tflop, and doing the math from the figures presented in that patent gives a figure of 4GHz. That's just a PREFERRED figure though, it's not set in stone. It could just be FUD from Sony to send ants down the pants of its competitors, making them scramble to try and match the performance.
Now, whenever companies have decided to take a more of a brainiac route than a speed demon route, they've tended NOT to meet their targets. This is a fairly well established trend, AFAIK.
Except, Cell isn't your typical MPU, so your trend goes out the window at square one, and even if you argue that you weren't thinking of Cell when you said that, well then what's the point of your argument? We could just as well start discussing the weather or something. You have to set an example into a scenario, or else it becomes MEANINGLESS.
"Lots of garlic often ruins a dish." True or false? Without knowing the specifics (like what you're cooking), it's impossible to tell! Some dishes are made with lots of garlic. Hence, set your statements into a scenario please, before you accuse me of not understanding them.
To resume my side of the argument, hehe, only Cell's performance can judge Cell's performance. Like I said, you can't predict one architecture's performance by looking at other, entirely unrelated architectures.
AMDs Athlon for example launched at 600MHz, faster than any then available PC CPU. It reached 1GHz faster than Intel did with the P3. It was arguably more brainiac than P3. However, these chips are very general in nature, Cell is not. It has a much more precisely specified architecture and instruction set. Each PU is probably not very brainy at all, there just happens to be a lot of them on one chip.
Cell will also not be required to scale up in clock speed as time passes, unlike a PC (or almost any other) CPU would be expected to. All that's required is that it can be manufactured with reasonable economics at target speed from the outset. Any further scaling headroom created from there on is simply gravy on top which can be put into further increasing yields and reducing power instead of improving clock speed...
I can't really see how you can say I didn't understand, when I understood perfectly.
SSEx is evolving with each iteration and one can't be sure what's going to happen to the number of flops generated. For all we know Tejas could bring in some significant boosts to the FPU -- if deemed necessary.
Dude, it's NOT going to be given such a boost. If Cell has 32PUs and each PU has four FMAC units (which I believe is the case in the patent, though I could be wrong, I'm not crazy enough to learn it word by word)... Well, let's just say you'd need quite a bit more than just a "significant boost" to match that. Also, don't forget bandwidth. Just adding SSE units isn't going to do you much good if you can't feed them.
Intel is scaling up the bus speed of the P4 (or P5 as tejas will probably be called), but it's not going to be close to the aggregate sum afforded by Cell, with its multiple local storages and eDRAM. We're talking about hundreds of GB/s in total here...! The P4 bus is set to scale to 400MHz (1200MHz equivalent considering quad datarate signalling), and that works out to no more than 12.6GB/s I think. Quite a bit less, wouldn't you say? It's less than just the Cell eDRAM bus interface actually, even at quite a bit less than 4GHz clockspeed that's preferred in the patent.
Additionally, there seems to be some rather interesting performance figures from the Pentium M, where it's FPU seems significantly faster -- 50% IIRC -- than the PIIIs on a clock for clock.
Except... P3 FPU is RATHER SLOW in comparison even to SSE2! Being 50% faster than that is no great achievement. P3 x87 performance is in low single-digit Gflops figures, which is no threat to anything.
But then again, the x86 market currently is trying to justify insane computing power for the average user -- they're succeeding of course.
Oh, just you wait for Longhorn... Microsoft is sure to find a good use for ALL of your MHzs with its bloated code...
In anycase, the 5 year figure just seems like something you've pulled out of your ass.
Do you TRULY foresee a 250+ Gflop x86 CPU within the next few years(say five, but I could just as well probably say five years AFTER PS3 has been released and still be safe)? Because I quite frankly DO NOT. No matter how much magic Intel does with Tejas, it's not going to come close to that level of computing power. Not even CLOSE. Even if they did add an insane number of SSE3 units, the chip would be starved of bandwidth and perform horribly in comparison to the chip real-estate all those execution units take up.
You gotta engineer a monster chip from the ground up to become a real monster, you can't just tack on more units and sort of hope for the best. Well, you COULD I guess, but Intel isn't stupid.
There is a possibility it's true, but if one followed one's common sense to conclusion, then they'd know that if there were any precieved threats, Intel is more than capable at stepping up.
Intel isn't seeing Cell as a competitior since Cell doesn't run x86 code. Hence they won't step up.
Possibly they'd create a derivate of Itanic to match or exceed Cell's FPU performance within the next five years, that would make sense since Itanic is already geared towards heavy flop-work. However, Itanic is not a x86 chip so it still doesn't count. It would still be quite hard work for them though, Itanic is far from 250Gflop/s performance, much less 1Tflop, and the same basic design hurdles have to be conquered with Itanic as with tejas to make it into such a beast, including solving the bandwidth issue.
Besides, I don't want to think of the horrific die size such a chip would have. With 6MB SRAM on it, Itanic is already a monstrously large processor, now tack on several hundred million transistors worth of FPU units...
*G*