NVIDIA Tegra Architecture

Surely this is a joke? Clearly that's the NV PR die shot and not 'and accurate image of the first silicon layer'. I think Rys is just continuing to have a laugh about how NV counts their 'cores'
 
Can somebody explain how it's possible to combine 28nm and 16nm transistors on the same piece of silicon, wouldn't that require the SoC being worked on by two different type of fabs?
 
I order that the joke doesn't spread any further as truth, I'll come clean: The image and subsequent analysis are completely fabricated. I recently finished the analysis of the real die shot and wanted to make a joke, because I now understand first-hand how bad the marketing image is, and how nonsensical some of the analysis of Tegra K1 is. Financial analysts with monetary stakes in NV and/or competitors getting the areas completely wrong, etc.

There is one piece of information in the shot that's correct if you know what you're looking at, but otherwise it's as made up as the original, as is the analysis in the same post, and the rest of my contribution to the thread after it.

You can mix transistor variants on the same wafer (LP + HPM for example), but you can't mix major nodes.

I think the joke was too convincing for some (and yeah, we edited Alexko's post to have less laughs to keep the joke going) :LOL: :LOL: :LOL:
 
I order that the joke doesn't spread any further as truth, I'll come clean: The image and subsequent analysis are completely fabricated. I recently finished the analysis of the real die shot and wanted to make a joke, because I now understand first-hand how bad the marketing image is, and how nonsensical some of the analysis of Tegra K1 is. Financial analysts with monetary stakes in NV and/or competitors getting the areas completely wrong, etc.

There is one piece of information in the shot that's correct if you know what you're looking at, but otherwise it's as made up as the original, as is the analysis in the same post, and the rest of my contribution to the thread after it.

You can mix transistor variants on the same wafer (LP + HPM for example), but you can't mix major nodes.

I think the joke was too convincing for some (and yeah, we edited Alexko's post to have less laughs to keep the joke going) :LOL: :LOL: :LOL:

Ah, I'm relieved (about my mental health). Apologies about almost killing the prank, I didn't think anyone would actually take it seriously.
 
I'm still working on it and should have more information to share in a few months.
Are those CPU cores actually to scale on their public "die shot," if you can even call it that? Nvidia obfuscates and doctors their Tegra die shots so heavily, that I can't help but feel like you've wasted your time.

GPU "cores" simply don't look like that in any GPU image I've ever seen. In fact, it's really hard (for me at least) to pick out the individual units in a GPU at a low level. Take this comparison of GK110 and GK104's SMX units:

JaXvZ.png


Supposedly, there are 192 ALUs in each of those images (anyone want to count? Doubt I'll get any takers ;)), coincidentally the same number as Tegra K1. Tegra K1's "die shot" has copy-pasted "artist's representations" of GPU cores.

Take a look at Tegra 3's actual die shot:
NVIDIA-Tegra-3-processor.jpg


And compare it to Nvidia's "artist's representation":
Tegra3_DIE_FRONTsm.jpg


Huh, where'd the companion core go? Well, Nvidia's die shots are complete bullshit.

The companion core is actually tucked in between the four cores (with some of the cache moved elsewhere, it seems, or it's using much denser cache, or it's omitted -- perhaps it doesn't have L2), not off on it's own like Nvidia portrays. The CPU cores themselves are also markedly different, showing that they're highly synthesized, with logic in "blobs," and not nice and pretty as Nvidia portrays.
I order that the joke doesn't spread any further as truth, I'll come clean: The image and subsequent analysis are completely fabricated. I recently finished the analysis of the real die shot and wanted to make a joke, because I now understand first-hand how bad the marketing image is, and how nonsensical some of the analysis of Tegra K1 is. Financial analysts with monetary stakes in NV and/or competitors getting the areas completely wrong, etc.

There is one piece of information in the shot that's correct if you know what you're looking at, but otherwise it's as made up as the original, as is the analysis in the same post, and the rest of my contribution to the thread after it.

You can mix transistor variants on the same wafer (LP + HPM for example), but you can't mix major nodes.

I think the joke was too convincing for some (and yeah, we edited Alexko's post to have less laughs to keep the joke going)
Aw man. Well, at least others can see why it was a farce.

I was hoping you had an actual die shot that you were hiding from us, and had actually determined the companion core to be that small.
 
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The real die is completely different to the marketing shot. The A15s are big (even the companion core), the SMX is visually distinct from the rest of the GPU, etc. I mean, even on the marketing picture you should instinctively know that there's more to a GPU than just ALUs. In this config of Kepler it might even be instinct that they might not dominate the area.
 
Anyway, I think he was just trying to see if he could fool a few people. There's some guys over there pumping Tegra K1 like it's the second coming of G80 or something.
The real die is completely different to the marketing shot. The A15s are big (even the companion core), the SMX is visually distinct from the rest of the GPU, etc. I mean, even on the marketing picture you should instinctively know that there's more to a GPU than just ALUs. In this config of Kepler it might even be instinct that they might not dominate the area.

Are you aware of any publicly available real die photos? I'd really like to see it. Heck, I wasn't even aware there was a real shot of Tegra 3 floating around until this morning.
 
Chipworks are usually the ones to publish the die shots, but AFAIK they haven't done that for Tegra K1, yet.
 
The real die is completely different to the marketing shot. The A15s are big (even the companion core), the SMX is visually distinct from the rest of the GPU, etc. I mean, even on the marketing picture you should instinctively know that there's more to a GPU than just ALUs. In this config of Kepler it might even be instinct that they might not dominate the area.

Despite that I fell for it (I'll hate you another time I'm too bored right now.... :LOL: ) in my idiotic layman's defense I did actually ask WTF TMUs, ROPs or FP64SPs are....
 
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