NVIDIA Kepler speculation thread

or Charlie is right about GK104 is 8 parts(2GPCs) and GK110 16parts(4GPCs)(since AMD still use 2 primitives/clk they maybe dont need to push themselves for quadros).. it fits 256bit/384 bit without decoupling ROPs..
another question again is 64bitx32 lanes cheaper than 128bitx16lanes interconnect?(i might be wrong please forgive me if it sounds naive, but what i am trying to say is, is doubling the each SMs bandwidth cheaper than keeping same bandwidth but doubling the SM count ?
 
fellix said:
Eight setup pipes in Kepler are actually not that far from plausible. Yes, 8 primitives per clock is probably an overkill by a wide margin, and the logic complexity too, but if NV is seeking an easy way to boost scan-out throughput, they could just use simpler setup units with half-rate speed (and 1/4 rate for consumer SKUs). This will keep the logic block size in check and will provide more optimized wiring to the SIMD multi-processors, avoiding critical hotspots.
Click to expand...
I certainly wouldn't mind it especially if they would closer to the theoretical troughput when compared to Fermi. (and open the triangle setup outside Quadro line.)
Quad fragment merging would be welcome addition as well and would certainly be huge help in highly tesselated scenes.
 
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Man from Atlantis said:
or Charlie is right about GK104 is 8 parts(2GPCs) and GK110 16parts(4GPCs)(since AMD still use 2 primitives/clk they maybe dont need to push themselves for quadros).. it fits 256bit/384 bit without decoupling ROPs..
Click to expand...

A block could mean anything and I'd say that SA worded it like that on purpose to keep it vague.

Assuming you'd have only 2 GPCs but also 1536SPs as I said in a former post a while ago I'm grateful I'm not a professional and wouldn't need to create a scheduler for something like that. Essentially you'd have 192SPs/SM and since I have severe doubts they'd go for more than 8 TMUs/SM it would also mean again just 64TMUs.

I realize that some aspects of my so far theoretical picture of the GK104 sound like overkill in a relative sense, but the whole enchilada makes way more sense then the scenario above; essentially its just a GF114 with a crapload of more SPs and for that I have an extremely hard time that it could beat let alone come close to a GF110. With 4 GPCs and 128TMUs at a higher frequency the former becomes far more believable.
 
Assuming 32 not-HC-SPs are as big as 16 HC-SPs:

4x GF114 (365mm², 1950M transitors)
- 128 TMUs
- 2x 256-Bit/2x32 ROPs
- some other stuff like redundant VPs, display-controllers, PCIe-controllers,...
+ DP-capability for 64 of 32SP-ALUs
+ some other new features
_______________________________
= 8GPC, 128 TMUs, 3072SPs (1:3 DP), 512-Bit, 64 ROPs in 550mm²@28nm ~ 6 billion transistors
 
more rumors@!
2008263dmycjnnoxjvjjl6.png

http://we.pcinlife.com/data/attachment/forum/201202/15/2008263dmycjnnoxjvjjl6.png

http://we.pcinlife.com/thread-1833778-1-1.html
 
jaredpace said:
more rumors@!
2008263dmycjnnoxjvjjl6.png

http://we.pcinlife.com/data/attachment/forum/201202/15/2008263dmycjnnoxjvjjl6.png

http://we.pcinlife.com/thread-1833778-1-1.html
Click to expand...

That makes absolutely no sense.
~8-9% performance between each product, unless 765 is an EOL product, aka limited supply, and is super close to a 770. In that case it goes back to a ~13% performance difference between products.

Also that is some bad scaling if big daddy is really 2x GK104. I am guessing it is more like 1.5x GK104.

Edit- Just notice the "announcement" date.
 
For me, if a "leak" compares to Tahiti, not to Fermi, then it's obvious propaganda. nV doesn't have control over driver developments for GCN, nor can't they guarantee they can match their pace. So when doing perf estimates, they should be refering to own cards.
 
DarthShader said:
For me, if a "leak" compares to Tahiti, not to Fermi, then it's obvious propaganda. nV doesn't have control over driver developments for GCN, nor can't they guarantee they can match their pace. So when doing perf estimates, they should be refering to own cards.
Click to expand...

There are too kinds of "leaks". The more serious ones that are aiming to reveal parts of the architecture mostly and on purpose false information because it's fun to toy with some of the happy go merry plagiarizers and let them ridicule themselves eventually. Depending on what anyone wants to believe from either or if you go out and say GK104 is by 40% faster than a GF110 (and yes those are free invented numbers for the sake of the example) there will always be someone that will immediately pick it up and run an "exclusive" newsblurb how GK104 is supposedly faster than Tahiti.

The most ironic thing is when anything as close as possible comes to the light of day and you've posted it for the first time chances are high that either/or IHVs PR representative will contact you in private asking where you've got it from. And that's already your first ever confirmation that you've hit a sensitive strain. If you're really serious about things like that you try to secure each bit of info from at least two independent reliable sources before you shoot off any kind of nonsense that might hit your way.

If you can read behind those lines above, it might help understanding a few things for the given case.
 
psurge said:
Well, Charlie seems to have recovered...
Click to expand...

To be honest, I missed the first part of the conference call, but I got the same impression from the second one. Charlie's wrong about the HDD thing, since AMD cited the same cause as the reason for their recent decrease in discrete GPU revenue, but other than that I think he makes good points.
 
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