Are you sure there aren't at least a few applications that do? After all, some HPC-oriented products weren't very good in DP. For instance IBM's Cell (first version), GT200, or even RV770. Granted, future versions of these products saw their DP performance greatly improved (except for RV770, so far anyway) but still.
Hell, there was even a G80-based Tesla card, even though G80 had no DP support at all (if I recall correctly).
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Errr wait a second....
http://www.xbitlabs.com/news/video/...epler_and_Maxwell_Architectures_Incoming.html
hkultala's point is legit above, but I'm obviously missing something in that statement too. Shouldn't it be more like 2.5-3 GFLOPs/Watt on Fermi?
http://www.xbitlabs.com/news/video/...epler_and_Maxwell_Architectures_Incoming.html
hkultala's point is legit above, but I'm obviously missing something in that statement too. Shouldn't it be more like 2.5-3 GFLOPs/Watt on Fermi?
DP fpu's use sp fpu's as well.
And TDP is expected to be the maximum power drawn, and not be workload dependent.
Well, unless you are going to count 0.0001% of HPC as non zero, HPC is DP only.
Although in many places SP could be fine. People just use DP as it gives less worries about accuracy, and at half rate, there's not much upside in risking low precision work.
May be they used the real power figures (and not the public ones) when they calculated that.
May be they used the real power figures (and not the public ones) when they calculated that.
ROFL
Jokes aside, either way I turn it the 1.5GFLOP/W doesn't make sense. A C2050 has 515 GFLOPs/s DP peak performance; it would need what ~344W to reach that DP performance?ROFL
You are right. With 250W for power, and 15 SMs and 1.4G clock, I get ~2.7GFlops/W.
May be this is their way of "achieving" a 4x increase in DP flops/W from Fermi to Kepler. :smile:
Too.In regard to the "big GPUs do good GPUs" statement it's notlike Nvidia has some choice. The thing is likely to ship in end 2011/2012, discrete GPUs in the low end will have disapeared and we don't know what AMD and Intel attitudes will be in regard to more the low/mid segment and the development of their fusion chips. Nvidia better have something impressive in the high end and so both on graphics and compute fronts.
Anyway I've a tough time believing those statement. Smells fishy.
OK, thanks!
I think this isn't that clear cut. Full speed DP makes no sense indeed. You need twice the operand fetch width, and for mul basically (more than) four times the multipliers. But, 2N sp could make sense if the cost of fetching operands is similar to the cost of the multiipliers themselves, since it requires the same fetch bandwidth (this is the SSE approach, obviously). Also, for adds it's easy to do half speed instead of quarter speed DP.
So really, AMD's approach makes sense. DP adds half speed (same fetch hw required as with twice the number of SP adds, not much more logic needed for the adders), DP mul (and hence mad) quarter speed (this "wastes" fetch hw, but very significant savings in the multipliers). If you have a really strong emphasis on DP, you can beef up your multipliers to be able to do half speed DP too, so you can utilize fetch hardware to the maximum extent - that is what nvidia has done for GF100 (and only GF100 not other Fermi chips). More than half speed DP makes absolutely no sense, and noone is going to try to do it (well, pretty sure of that - it would be crazy).
Could it be that they were talking about "sustained" FLOPS/W and not peak? Maybe we're just over-analyzing NVIDIA's bullsh*t…
Like?
And as I said, if you have half rate DP, then what is the upside of using single precision?
Also, in my experience, people just tend to shrug and use DP throughout just out of habit. May be you can share some of your experiences.
http://www.realworldtech.com/page.cfm?ArticleID=RWT050310102525
That's just one I can reference off the top of my head.
David
Blazkowicz
Legend
actually the whole idea of paperflops per watt is weird, if you go through that kind of thinking.
Would you consider distributed computing projects as HPC, or only centralized systems? If the former, DC projects such as Folding @ Home make significant use of SP FLOPs, at least when using GPUs.
That's one data point. HPC's bigger than that.
I thought there was a class of HPC apps which used single precision. Perhaps air quality simulations are fine with HPC.
BTW, in your discussions with the authors, did you ask about why they used SP? What did they say? And did they consider the possible accuracy issues?
I thought there was a class of HPC apps which used single precision. Perhaps air quality simulations are fine with HPC.
BTW, in your discussions with the authors, did you ask about why they used SP? What did they say? And did they consider the possible accuracy issues?
