NVIDIA Kepler speculation thread

[KimB]

Well, I definitely think that the focus on performance/watt should be a tremendous boon to nVidia's next architecture.

Please bear in mind that nVidia has shown itself to be quite good at directly tackling the shortcomings of its previous architectures, and given that power consumption is the obvious shortcoming of Fermi, I don't much doubt that there will be big improvements in perf/watt for their next architecture. Some points to bear in mind:

1. They may increase perf/watt significantly, but if ATI does an even better job, it will be perceived as a failure. It will be interesting to see how this plays out, at the very least.
2. Improving performance per watt doesn't mean that overall power consumption will go down. Likely it will remain about the same for a given price bracket, but performance will increase.
3. Delays are common and should surprise no one.

 

[Alexko]

Well, I definitely think that the focus on performance/watt should be a tremendous boon to nVidia's next architecture.

Please bear in mind that nVidia has shown itself to be quite good at directly tackling the shortcomings of its previous architectures, and given that power consumption is the obvious shortcoming of Fermi, I don't much doubt that there will be big improvements in perf/watt for their next architecture. Some points to bear in mind:

1. They may increase perf/watt significantly, but if ATI does an even better job, it will be perceived as a failure. It will be interesting to see how this plays out, at the very least.
2. Improving performance per watt doesn't mean that overall power consumption will go down. Likely it will remain about the same for a given price bracket, but performance will increase.
3. Delays are common and should surprise no one.

I don't know if there really is going to be such a significant improvement in perf/W for Kepler (beyond what you would get from 28nm alone) because I think NVIDIA discovered that Fermi's power draw was so huge pretty late. Of course this is the kind of thing you can simulate, but probably not nearly as accurately as performance/clock. Even pretty close to launch, they released specifications for Tesla that proved to be overly optimistic, power-wise.

So the question is: when NVIDIA discovered how bad Fermi's performance/W was, was that early enough to significantly affect Kepler?

Obviously, Maxwell is a different story.

 

[dkanter]

That's one data point. HPC's bigger than that.

I thought there was a class of HPC apps which used single precision. Perhaps air quality simulations are fine with HPC.

BTW, in your discussions with the authors, did you ask about why they used SP? What did they say? And did they consider the possible accuracy issues?

They used SP because they don't need more accuracy and it will double your performance...

Pretty straight forward.

David

 

[KimB]

So the question is: when NVIDIA discovered how bad Fermi's performance/W was, was that early enough to significantly affect Kepler?

I would tend to expect so. They would have noticed the discrepancy a number of months before launch, after all. That's likely a good 1.5-2 years ahead of the final tape out date for Kepler, which should be enough time to make some significant changes, though only just.

Also bear in mind that the fact that power would be very important for Kepler would have been apparent even before the launch of Fermi.

At any rate, I wouldn't really expect nVidia to do poorly here. They may still get beat by ATI, but I'm expecting at least some perf/watt improvements beyond just process improvements.

 

[CarstenS]

WRT to that: I don't think it's a coincidence that Nvidia appointed Bill Dally chief scientist mid-2009. After all, (one of) his area(s) of expertise is making networked processors talk to each other.

 

[trinibwoy]

Why are you guys talking as if Fermi's high power consumption was built into the design? Obviously they didn't aim for the current state of affairs.

 

[Dave Baumann]

Why are you guys talking as if Fermi's high power consumption was built into the design? Obviously they didn't aim for the current state of affairs.

The size of the ASIC tells me that it absolutely was designed for the power envolope that its operating in.

 

[no-X]

Really? It's smaller, yet more power hungry than GT200...

 

[digitalwanderer]

Anyone else just trying real hard to figure out how to tie in Kepler to the Keebler Elves for ridicule purposes? :|

 

[Kaotik]

Really? It's smaller, yet more power hungry than GT200...

And on different, smaller process with different power characteristics, the comparison is invalid.

 

[BRiT]

Anyone else just trying real hard to figure out how to tie in Kepler to the Keebler Elves for ridicule purposes? :|

No, but there's plenty of Kepler's Third Law jokes to go around...

Spoiler

Small ePenis attracted to big GPUs

.

 

[no-X]

And on different, smaller process with different power characteristics, the comparison is invalid.

Really? ATi's 40nm GPUs are bigger, yet less power hungry than their previous generation, so power consumption is NOT related only to die size.

During summer 2009 nVidia's PR noted, that they are expecting power consumption about 10% lower than for GT200...

 

[caveman-jim]

Anyone else just trying real hard to figure out how to tie in Kepler to the Keebler Elves for ridicule purposes? :|

I wasn't, but...

 

[trinibwoy]

The size of the ASIC tells me that it absolutely was designed for the power envolope that its operating in.

The size alone doesn't tell you that at all, considering there have been larger chips in smaller power envelopes. You mean Nvidia included the following goals in their Fermi design?

-no fully enabled chips
-miss clock targets by at least 50Mhz
-require a monstrous air cooler just to keep the thing under control
-still end up with high temperatures and power consumption to be ridiculed by the masses

To suggest that things worked out as planned is downright laughable.

 

[Dave Baumann]

Like I said, I think the power is on more or less where they aimed for. Whether or not performance was is a different thing.

 

[trinibwoy]

None of the things I mentioned there have anything to do with performance. You're saying they aimed for their power consumption and cooling needs to be out of control but it would've been ok if performance targets were met? Ummm, yeah that makes no sense Dave.

 

[Dave Baumann]

Target TDP's is one of the design criteria when you build a chip because you have eventual product targets for that chip. When the chip comes back and you find out how far or close you are to the pre-silicon targets you make choices on what to do for the products, which may involve scaling back in performance. Given all the Fermi based products out there, I don't see any that are not operating in the TDP product ranges you are likely to plan for such products.

 

[trinibwoy]

They only managed to get "down" to an acceptable (yet still impressive) TDP by disabling parts of the chip and strapping on a herculean cooling assembly. How can you also claim that those measures were part of their plan? That's like saying I cut off my arm to avoid gangreen but that's ok since I had planned to lose that arm anyway.

 

[neliz]

They only managed to get "down" to an acceptable (yet still impressive) TDP by disabling parts of the chip and strapping on a herculean cooling assembly. How can you also claim that those measures were part of their plan? That's like saying I cut off my arm to avoid gangreen but that's ok since I had planned to lose that arm anyway.

You make it sound bad!

They set out to make a chip that's 529mm2, has a TDP of ~300W and is blazing fast.
They ended up scoring two out of three.

So in good NV sense, we will probably see Kepler at GPUTC2011, and have the "kicker" come up somewhere in Q1 (CES?)
But seeing how they already failed to deliver their promised 8x better DP in Fermi over Tesla, I don't think we have to get that excited about the numbers they showed here (25% is salted.)

 

[Harison]

They only managed to get "down" to an acceptable (yet still impressive) TDP by disabling parts of the chip and strapping on a herculean cooling assembly. How can you also claim that those measures were part of their plan? That's like saying I cut off my arm to avoid gangreen but that's ok since I had planned to lose that arm anyway.

You are just nitpicking. And bigger part of disabling parts wasnt TDP, but yields. As Dave said, when you plan chip, you try to meet for all main goals - size, TDP, performance and features targets. Some may fall short of expectations, thats a life of any manufacturer.